Patents Assigned to Taiwan Semiconductor Manufacturing Company, Ltd.
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Publication number: 20240136324Abstract: A semiconductor manufacturing method is provided. The semiconductor manufacturing method includes the following steps. A first semiconductor element with a bonding film and a first stressing film is formed. The first bonding film and the first stressing film are formed on two opposite sides of the first semiconductor element. The first stressing film makes the first bonding film to have a first convex surface. A second semiconductor element with a second bonding film is formed. The second bonding film is formed on one side of the second semiconductor element. The first semiconductor element and the second semiconductor element are bonded by bonding the first bonding film and the second bonding film.Type: ApplicationFiled: January 19, 2023Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih CHIOU, Yen-Ming CHEN, Yung-Chi LIN
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Publication number: 20240138156Abstract: Semiconductor devices are provided. First and second dies are vertically stacked. The first die includes a plurality of memory cells and a plurality of first and second connection features. The memory cells are arranged in rows and columns of a memory array. The first connection features are electrically connected to a plurality of word lines of the memory array. The second connection features are electrically connected to a plurality of bit lines of the memory array. Each third connection feature of the second die is electrically connected to a respective first connection feature. Each word line driver of the second die is electrically connected to a respective third connection feature. Each fourth connection feature of the second die is electrically connected to a respective second connection feature of the first die. Each sense amplifier of the second die is electrically connected to a respective fourth connection feature.Type: ApplicationFiled: March 3, 2023Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Han-Jong CHIA
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Publication number: 20240138153Abstract: A ferroelectric memory device and a memory array are provided. The ferroelectric memory device includes a word line; a pair of source/drain electrodes, a channel layer, a work function layer and a ferroelectric layer. The source/drain electrodes are disposed at opposite sides of the word line, and elevated from the word line. The channel layer has a bottom planar portion and wall portions. The bottom planar portion extends along a top surface of the word line, and opposite ends of the bottom planar portion are connected to sidewalls of the source/drain electrodes through opposite ones of the wall portions. The work function layer is electrically connected to the word line, and extends along the bottom planar portion and the wall portions of the channel layer. The ferroelectric layer separates the channel layer from the work function layer.Type: ApplicationFiled: March 5, 2023Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chia-En Huang, Sai-Hooi Yeong
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Publication number: 20240136199Abstract: A semiconductor device and a semiconductor manufacturing method thereof are provided. The semiconductor manufacturing method includes the following streps. A first semiconductor element with a first bonding film is formed. The first bonding film is formed on a first side of the first semiconductor element. The first semiconductor element and the first bonding film form a taper structure. The first bonding film forms a wide portion of the taper structure. The first semiconductor element forms a narrow portion of the taper structure. A second semiconductor element with a second bonding film is formed. The second bonding film is formed on the second semiconductor element. The first semiconductor element and the second semiconductor element are bonded by bonding the first bonding film and the second bonding film. An oxide layer is filled to surround the first semiconductor element and the first bonding film.Type: ApplicationFiled: January 20, 2023Publication date: April 25, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chi LIN, Tsang-Jiuh WU, Wen-Chih CHIOU
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Publication number: 20240136293Abstract: Provided are a package structure having a joint structure and a method of forming the same. The package structure includes: a first under bump metallurgy (UBM) structure disposed on a first dielectric layer, wherein the first UBM structure at least comprises: a barrier layer embedded in the first dielectric layer; and an upper metal layer disposed over the barrier layer, wherein a sidewall of the barrier layer is laterally offset outward from a sidewall of the upper metal layer, and a portion of a top surface of the barrier layer is exposed by the first dielectric layer; and a solder layer disposed on the first UBM structure and contacting the upper metal layer.Type: ApplicationFiled: January 31, 2023Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Wen-Chih Chiou, Ying-Ching Shih
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Publication number: 20240134266Abstract: A reflective mask includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an intermediate layer disposed over the capping layer, an absorber layer disposed over the intermediate layer, and a cover layer disposed over the absorber layer. The absorber layer includes one or more layers of an Jr based material, a Pt based material or a Ru based material.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yun-Yue LIN
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Publication number: 20240136316Abstract: A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
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Publication number: 20240134293Abstract: A semiconductor processing method includes: selecting a target state of a reticle based on a given data set, wherein the given data set comprises temperature profiles of the reticle correlated to a target overlay performance, and the target state is a state in which a deformation of the reticle is substantially unchanged; regulating the reticle to reach the target state; and performing an exposure process on a target workpiece by using the reticle.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yueh-Lin Yang, Chi-Hung Liao
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Publication number: 20240136251Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.Type: ApplicationFiled: January 4, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
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Publication number: 20240133841Abstract: A bio-field effect transistor (bioFET) system includes a bioFET configured to receive to a first voltage signal and output a current signal, where the current signal varies exponentially with respect to the first voltage signal. A logarithmic current-to-time converter is connected to the bioFET and is configured to receive the current signal and convert the current signal to a time domain signal. The time domain signal varies logarithmically with respect to the current signal, such that the time domain signal varies linearly with respect to the first voltage signal.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jie Huang, Jui-Cheng Huang
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Publication number: 20240136441Abstract: A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.Type: ApplicationFiled: February 5, 2023Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ken-Ichi Goto, Cheng-Yi Wu
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Publication number: 20240136246Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
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Publication number: 20240133942Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao Chen, Mill-Jer Wang
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Publication number: 20240134279Abstract: A photoresist includes a solvent, a polymer and an additive. The polymer is dissolved in the solvent, and the additive is dispersed in the solvent. The additive includes a double bond or includes an epoxy group. The additive has a surface tension different from a surface tension of the polymer.Type: ApplicationFiled: March 27, 2023Publication date: April 25, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Hsin HSIEH, Wei-Han LAI, Ching-Yu CHANG
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Publication number: 20240136008Abstract: A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell. The reference voltage generator is configured to generate a reference voltage based on a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage, and the reference voltage generator comprises a resistor that is configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hung-Chang Yu
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Publication number: 20240136383Abstract: A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
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Publication number: 20240136427Abstract: A semiconductor structure includes a channel structure, a gate structure, two source/drain features, and a plurality of inner spacers. The channel structure includes a plurality of channel features which are spaced apart from each other. The gate structure is disposed to surround the channel features. The source/drain features are disposed at two opposite sides of the channel structure such that each of the channel features interconnects the source/drain features. Each of the inner spacers is disposed to separate the gate structure from a corresponding one of the source/drain features. Each of the inner spacers includes an inner spacer body and a lateral nitrided portion. The lateral nitrided portion is in direct contact with the corresponding one of the source/drain features and has a nitrogen content greater than that of the inner spacer body.Type: ApplicationFiled: January 13, 2023Publication date: April 25, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Man-Nung SU, I-Hsuan LO
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Patent number: 11966165Abstract: A bottom lens for an immersion exposure tool includes a hydrophobic coating on the sidewalls of the bottom lens. A bottom portion of the bottom lens is not coated with the hydrophobic coating to maintain the optical performance of the bottom lens and to not distort a pattern that is to be transferred to a substrate. The hydrophobic coating may reduce the thermal instability of the bottom lens. This may reduce overlay variation during operation of the immersion exposure tool, which may increase manufacturing yield, decrease device failures, and/or decrease rework and repairs.Type: GrantFiled: January 22, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yung-Yao Lee
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Patent number: 11967611Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.Type: GrantFiled: May 30, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hai-Dang Trinh, Yi Yang Wei, Fa-Shen Jiang, Bi-Shen Lee, Hsun-Chung Kuang
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Patent number: 11964358Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.Type: GrantFiled: March 19, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Yu Wang, Chun-Hao Kung, Ching-Hsiang Tsai, Kei-Wei Chen, Hui-Chi Huang