Abstract: A method for manufacturing a semiconductor includes: receiving a photomask substrate including a shielding layer; defining a chip region and a peripheral region adjacent to the chip region; forming a design pattern in the chip region; forming a reference pattern by emitting one first radiation shot and a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is greater than a pixel size of the second radiation shot; comparing a reference roughness of a boundary of the reference pattern and a beta roughness of a boundary of the beta pattern; transferring the design pattern to the shielding layer if a difference between the reference roughness and the beta roughness is within a tolerance; and transferring the design pattern of the photomask to a semiconductor substrate.

Abstract: A semiconductor structure includes a substrate; a sensing device disposed over the substrate and including a plurality of protruding members protruded from the sensing device; a sensing structure disposed adjacent to the sensing device and including a plurality of sensing electrodes protruded from the sensing structure towards the sensing device; and an actuating structure disposed adjacent to the sensing device and configured to provide an electrostatic force on the sensing device based on a feedback from the sensing structure. Further, a method of manufacturing the semiconductor structure is also disclosed.

Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect disposed within a dielectric structure over a substrate. A memory device includes a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the lower interconnect. A sidewall spacer includes an interior sidewall that continuously extends from along an outermost sidewall of the top electrode to below an outermost sidewall of the bottom electrode. The sidewall spacer further includes an outermost sidewall that extends from a bottom surface of the sidewall spacer to above a top of the bottom electrode.

Abstract: Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate connected to the second node. A second NMOS transistor is coupled between the first node and the ground, a gate connected to the first node, and has a gate connected to the first node. Sources of the first and second PMOS transistors share a P+ doped region in N-type well region, and the first PMOS transistor is disposed between the second PMOS transistor and the first and second NMOS transistors.

Abstract: A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. Each level shifter is configured to output a corresponding phase clock signal of the first set of phase clock signals. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to at least one of a first or second phase clock signal of the first set of phase clock signals or a set of control signals. The first clock output signal has a second duty cycle. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

Abstract: A method for cell swapping is provided. A location for swapping a first cell is determined. One or more legal positions for cell placement are determined at the location. A plurality of cells is determined for of the plurality of legal positions. A second cell from the plurality of cells is determined based on timing information associated with each of the plurality. The first cell is swapped with the second cell.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor fin structure over a substrate, forming a dielectric fin structure laterally spaced apart from the semiconductor fin structure, forming a source/drain spacer between the semiconductor fin structure and the dielectric fin structure, etching an upper portion of the semiconductor fin structure to expose a lower portion of the semiconductor fin structure, and forming a source/drain feature over the lower portion of the semiconductor fin structure. The source/drain spacer is interposed between the source/drain feature and the dielectric fin structure.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin having a first portion having a first width and a second portion having a second width substantially less than the first width. The first portion has a first surface, the second portion has a second surface, and the first and second surfaces are connected by a third surface. The third surface forms an angle with respect to the second surface, and the angle ranges from about 90 degrees to about 130 degrees. The structure further includes a gate electrode layer disposed over the semiconductor fin and source/drain epitaxial features disposed on the semiconductor fin on opposite sides of the gate electrode layer.

Abstract: A tool and methods of removing films from bevel regions of wafers are disclosed. The bevel film removal tool includes an inner motor nested within an outer motor and a bevel brush secured to the outer motor. The bevel brush is adjustable radially outward to allow the wafer to be inserted in the bevel brush and to be secured to the inner motor. The bevel brush is adjustable radially inward to engage one or more sections of the bevel brush and to bring the bevel brush in contact with a bevel region of the wafer. Once engaged, a solution may be dispensed at the engaged sections of the bevel brush and the inner motor and the outer motor may be rotated such that the bevel brush is rotated against the wafer such that the bevel films of the wafer are both chemically and mechanically removed.

Abstract: An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed over the first substrate; and a second substrate disposed over the dielectric layer. The second substrate includes anchor regions comprising silicon extending upwards from the dielectric layer, and a series of interdigitated fingers extend from inner sidewalls of the anchor regions. The interdigitated fingers extend generally in parallel with one another in a first direction and have respective finger lengths that extend generally in the first direction. A plurality of peaks comprising silicon is disposed on the dielectric layer directly below the respective interdigitated fingers. The series of interdigitated fingers are cantilevered over the plurality of peaks. A first peak is disposed below a base of a finger and has a first height, and a second peak is disposed below a tip of the finger and has a second height less than the first height.

Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.

Abstract: The present disclosure relates an integrated chip. The integrated chip may include a semiconductor substrate having sidewalls that define a plurality of fins. A dielectric material is arranged between the plurality of fins and a gate structure is disposed over the dielectric material and around the plurality of fins. Epitaxial source/drain regions are disposed along opposing sides of the gate structure and respectively include a plurality of source/drain segments disposed on the plurality of fins and a doped epitaxial material disposed onto and between the plurality of source/drain segments. A first source/drain segment of the plurality of source/drain segments laterally extends in opposing directions to different distances past opposing sides of an underlying first fin of the plurality of fins.

Abstract: An electronic assembly and a manufacturing method thereof are provided. The electronic assembly includes a carrier substrate including a flexible structure and a circuit structure, and an electronic device disposed on the circuit structure. The flexible structure includes a first dielectric layer and a conductive pattern overlying thereon. The circuit structure includes a second dielectric layer overlying the first dielectric layer and the conductive pattern, and a circuit layer disposed on and passing through the second dielectric layer to be in contact with the conductive pattern, the first flexible structure includes a first portion embedded in the circuit structure and a second portion connected to the first portion and extending out from an edge of the circuit structure. The electronic device includes chip packages electrically coupled to the flexible structure through the circuit structure, and is sized to substantially match a size of the first portion of the circuit structure.