Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: A memory device includes a memory array comprising a plurality of memory cells arranged over a plurality of rows, the rows including a plurality of word lines, respectively, a first group of the memory cells coupled to an even-numbered one of the word lines and a second group of the memory cells coupled to an odd-numbered one of the word lines. The even-numbered word line is disposed in a first one of a plurality of metallization layers formed vertically above a substrate, wherein the even-numbered word line extends along a first lateral direction and includes a first stitch portion extending in a second lateral direction perpendicular to the first lateral direction. The odd-numbered word line is disposed in a second one of the plurality of metallization layers, wherein the odd-numbered word line extends along the first lateral direction and includes a second stitch portion extending in the second lateral direction.

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a photonic integrated circuit component, an electric integrated circuit component, a lens and an optical signal port. The photonic integrated circuit component comprises an optical input/output portion configured to transmit and receive optical signal. The electric integrated circuit component is electrically connected to the photonic integrated circuit component. The lens is disposed on a sidewall of the photonic integrated circuit component. The optical signal port is optically coupled to the optical input/output portion.

Abstract: An overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. The method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. The second sub-patterns are disposed interleaved between the first sub-patterns. The method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.

Abstract: A computer readable medium comprising computer executable instructions for carrying out a method is disclosed. The method includes: generating a schematic of an integrated circuit including a plurality of components, each of the components associated with a format, the format indicating a matching group that represents a respective circuit functionality; merging a first device array layout, which corresponds to a first subset of the components that share a first matching group, and a second device array layout, which corresponds to a second subset of the components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer enclosing the third device array layout; inserting dummy patterns surrounding the first layer; and inserting a guard ring further surrounding the dummy patterns.

Abstract: A bonding tool for bonding semiconductor dies to a semiconductor wafer is provided. The bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. The wafer chuck carries the semiconductor wafer and the semiconductor dies placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor dies are laterally surrounded by the edge support, and a top surface of the edge support substantially levels with surfaces of the semiconductor dies. The hard plate is movably disposed over the semiconductor dies, the edge support and the wafer chuck. The buffer layer is disposed on a bottom surface of the hard plate, and the buffer layer is in contact with the top surface of the edge support and the semiconductor dies when the hard plate moves towards the edge support.

Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)?2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.

Abstract: A semiconductor device and method for fabricating a semiconductor device includes etch selectivity tuning to enlarge epitaxy process windows. Through modification of etching processes and careful selection of materials, improvements in semiconductor device yield and performance can be delivered. Etch selectivity is controlled by using dilute gas, using assistive etch chemicals, controlling a magnitude of bias power used in the etching process, and controlling an amount of passivation gas used in the etching process, among other approaches. A recess is formed in a dummy fin in a region of the semiconductor where epitaxial growth occurs to further enlarge the epitaxy process window.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a well, a plurality of channel sheets, a source/drain region, a contact, a gate electrode, a gate dielectric layer and a spacer. The gate electrode includes at least one inner gate electrode and a top gate electrode. The inner gate electrode is located between the plurality of channel sheets. The top gate electrode is located upon a top of the plurality of channel sheets. The top gate electrode includes a first stage top gate and a second stage top gate. The first stage top gate is stacked on the second stage top gate, and a first gate length of the first stage top gate is less than a second gate length of the second stage top gate. The gate dielectric layer surrounds the gate electrode. The spacer includes at least one inner spacer and a top spacer.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a first die, a second die and a redistribution layer structure. The first die and the second die are disposed laterally. The redistribution layer structure is disposed over and electrically connected to the first die and the second die. The redistribution layer structure includes a plurality of vias and a plurality of lines stacked alternately and electrically connected to each other and embedded by a plurality of polymer layers. The redistribution layer structure further includes a first pad overlapped with the first die and a second pad overlapped with the second die. The first pad, the second pad and lines closest to the first die and the second die are located at substantially the same level, and from a top view, the first pad and the second pad have different shapes.

Abstract: A manufacturing method of a package structure includes: forming a first package component, where the first package component includes a first insulating encapsulation laterally covering semiconductor dies and a redistribution structure formed on the first insulating encapsulation and the semiconductor dies; coupling the first package component to a second package component; forming an underfill layer between the first and second package component, where the underfill layer extends to cover a sidewall of the first package component; forming a metallic layer on opposing surfaces of the semiconductor dies and the first insulating encapsulation by using a jig, where a window of the jig accessibly exposes the opposing surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the opposing surface of the first insulating encapsulation is shielded by the jig.

Abstract: A manufacturing method includes the following steps: forming a semiconductor structure, wherein the semiconductor structure comprises a wafer, a plurality of dummy gates and a dielectric layer, and the dummy gates are formed on the wafer, and the dielectric layer is formed on the dummy gates; forming an epitaxy layer between adjacent two of the dummy gates, wherein there is a nodule remained on the dielectric layer in process of forming the epitaxy layer; and removing the nodule by using an ultrashort laser beam.

Abstract: A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: In a method of manufacturing a semiconductor device, a first conductive pattern is formed in a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive pattern and the first ILD layer, a via contact is formed in the second ILD layer to contact an upper surface of the first conductive pattern, a second conductive pattern is formed over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view, a part of the via contact is etched by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ILD layer, and a third ILD layer is formed over the second ILD layer.

Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.

Abstract: The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion below the gate spacer layer and a second portion below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.

Abstract: A method of manufacturing an extreme ultraviolet mask, including forming a multilayer Mo/Si stack including alternating Mo and Si layers over a first major surface of a mask substrate, and forming a capping layer over the multilayer Mo/Si stack. An absorber layer is formed on the capping layer, and a hard mask layer is formed over the absorber layer. The hard mask layer is patterned to form a hard mask layer pattern. The hard mask layer pattern is extended into the absorber layer to expose the capping layer and form a mask pattern. A border pattern is formed around the mask pattern. The border pattern is extended through the multilayer Mo/Si stack to expose the mask substrate and form a trench surrounding the mask pattern. A passivation layer is formed along sidewalls of the trench.