Patents Assigned to Taiwan Semiconductor Manufacturing Company, Ltd.
  • Patent number: 11929348
    Abstract: A multi-die apparatus includes a plurality of die groups. Each die group includes a plurality of dies stacked parallel to each other and with an edge surface of each die aligned with a planar side surface. The multi-die apparatus also includes a base substrate structure that has a planar top surface characterized by a given direction of lattice crystalline planes. Each of the plurality of die groups is disposed sideways on the base substrate structure, with the planar side surface of each die group bonded to the planar top surface of the base substrate structure. One or more of the plurality of die groups are arranged in a non-parallel manner relative to the given direction of lattice crystalline planes of the base substrate structure.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jen-Yuan Chang
  • Patent number: 11930717
    Abstract: A synthetic antiferromagnetic structure for a spintronic device is disclosed and has an FL2/Co or Co alloy/antiferromagnetic coupling/Co or Co alloy/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. Antiferromagnetic coupling is improved by inserting a Co or Co alloy dusting layer on top and bottom surfaces of the antiferromagnetic coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)n laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the synthetic antiferromagnetic structure.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Robert Beach, Guenole Jan, Yu-Jen Wang, Ru-Ying Tong
  • Patent number: 11929322
    Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Li-Hsien Huang
  • Patent number: 11930716
    Abstract: A ferromagnetic layer is capped with a metallic oxide (or nitride) layer that provides a perpendicular-to-plane magnetic anisotropy to the layer. The surface of the ferromagnetic layer is treated with a plasma to prevent diffusion of oxygen (or nitrogen) into the layer interior. An exemplary metallic oxide layer is formed as a layer of metallic Mg that is plasma treated to reduce its grain size and enhance the diffusivity of oxygen into its interior. Then the plasma treated Mg layer is naturally oxidized and, optionally, is again plasma treated to reduce its thickness and remove the oxygen rich upper surface.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guenole Jan, Ru-Ying Tong
  • Patent number: 11929321
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11930715
    Abstract: A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 11927628
    Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chu-Feng Liao, Hung-Ping Cheng, Yuan-Yao Chang, Shuo-Wen Chang
  • Patent number: 11929261
    Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
  • Patent number: 11929113
    Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Atul Katoch, Adrian Earle
  • Patent number: 11929109
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Patent number: 11930645
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a first and a second contact plug, a first metal via, a magnetic tunneling junction (MTJ) structure, and a metal interconnect. The transistor region includes a gate over the substrate, and a first and a second doped regions at least partially in the substrate. The first and the second contact plug are over the transistor region. The first and the second contact plug include a coplanar upper surface. The first metal via and the MTJ structure are over the first and the second contact plug, respectively. The first metal via is leveled with the MTJ structure. The metal interconnect is over the first metal via and the MTJ structure, and the metal interconnect includes at least two second metal vias in contact with the first metal via and the MTJ structure, respectively.
    Type: Grant
    Filed: March 5, 2023
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang
  • Patent number: 11929258
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 11929110
    Abstract: A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuits coupled to a first set of memory cells that is configured to store a first set of data. The global control circuit is configured to generate a first and second set of global pre-decoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first and second set of local pre-decoder signals in response to the corresponding first and second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to the first set of local address signals and the first clock signal.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sanjeev Kumar Jain, Ishan Khera, Atul Katoch
  • Patent number: 11929417
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 11929116
    Abstract: A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
  • Patent number: 11929128
    Abstract: A circuit includes an operational amplifier including an inverting input terminal capacitively coupled to each of an OTP cell array and an NVM cell array and first and second output terminals, an ADC coupled to the first and second output terminals, thereby configured to receive a differential output voltage from the operational amplifier, and a comparator coupled to the ADC and configured to output a data bit responsive to a digital output signal received from the ADC. The circuit is configured to cause the operational amplifier to generate the differential output voltage based on each of a current received from an OTP cell of the OTP cell array and a voltage received from an NVM cell of the NVM cell array.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chih-Min Liu
  • Patent number: 11929409
    Abstract: Semiconductor device includes a substrate having multiple fins formed from a substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin, a second epitaxial layer formed on the first epitaxial layer, and a third epitaxial layer formed on the second epitaxial layer, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion; a fourth epitaxial layer formed on the third epitaxial layer, a second source/drain feature adjacent the first source/drain feature, comprising a first epitaxial layer in contact with a second fin, a second epitaxial layer formed on the first epitaxial layer of the second source/drain feature, a third epitaxial layer formed on the second epitaxial layer of the second source/drain feature, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion of the third epitaxial layer of the second source/drain feature; a
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11929333
    Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Tzu-Chun Tang, Chieh-Yen Chen, Che-Wei Hsu
  • Patent number: 11929413
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a second gate stack over the second channel structure. The second gate stack has a protruding portion extending away from the second channel structures. The protruding portion of the second gate stack has a second width, and half of the first width is greater than the second width.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Chuan You, Huan-Chieh Su, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11929267
    Abstract: An ultraviolet (UV) lamp assembly of a UV curing tool is provided for curing a low dielectric constant (low-k) material layer of a semiconductor wafer. The UV lamp assembly includes: a UV lamp which emits UV light; a first reflector arranged proximate to a first side of the UV lamp, the first reflector including a first surface facing the UV lamp from which UV light emitted by the UV lamp is at least partially reflected; and a UV reflective coating partially coating the first surface of the reflector. Suitably, a plurality of areas of the first surface of the reflector remain uncoated with the UV reflective coating and the plurality of uncoated areas are arranged to promote a uniform exposure of the semiconductor wafer to UV irradiation.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chun Hu, Kuang-Wei Cheng, Chyi-Tsong Ni