Abstract: A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.

Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.

Abstract: A memory circuit and a method for reading a memory circuit are provided. The memory circuit includes reference memory cells and operation memory cells. The method includes reading a selected reference memory cell at a first time to get a first voltage; reading the selected reference memory cell at a second time after the first time to get a second voltage; adjusting a read voltage of the memory cell to be an adjusted read voltage of the memory cell according to the voltage difference between the first voltage and the second voltage; applying the adjusted read voltage on a selected operation memory cell corresponding to the selected reference memory cell; and applying the adjusted read voltage on other selected operation memory cells in a same row of the memory array corresponding to the selected reference memory cell.

Abstract: A memory device includes a plurality of memory cells disposed over a substrate and formed as an array that has a plurality of rows and a plurality of columns. Each of the plurality of memory cells includes a plurality of transistors. A first subset of the plurality of memory cells, that are disposed in first neighboring ones of the plurality of rows, are physically coupled to a corresponding one of a plurality of second interconnect structures that carries a supply voltage through a corresponding one of a plurality of first interconnect structures. The plurality of first interconnect structures extend along a first lateral direction in parallel with a lengthwise direction of a channel of each of the transistors of the memory cells, and the plurality of second interconnect structures, disposed above the plurality of first interconnect structures, extend along a second lateral direction perpendicular to the first lateral direction.

Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.

Abstract: A semiconductor device and a method for manufacturing an interconnecting metal layer thereof are provided. The semiconductor device includes a gate layer, a dielectric layer, an insulating layer, an epitaxial layer, and a sidewall liner. The dielectric layer is disposed on one side of the gate layer, the insulating layer is disposed on another side of the gate layer, the epitaxial layer is located on the insulating layer, and the sidewall liner penetrates the dielectric layer and the gate layer, and one end of the sidewall liner is connected to the epitaxial layer. The sidewall liner is converted from a high-k material to a low-k material by hydrogen and oxygen plasma treatments.

Abstract: An interconnect structure is provided. The interconnect structure includes a transistor on a substrate, a first dielectric layer over the transistor, a first metal line through the first dielectric layer, a second dielectric layer over the first dielectric layer, and a via through the second dielectric layer and on the first metal line. A first side surface of the first dielectric layer includes a first portion in direct contact with the first metal line and a second portion in direct contact with the via, and the first portion of the first side surface of the first dielectric layer is aligned with the second portion of the first side surface of the first dielectric layer.

Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.

Abstract: A device includes first and second gate structures respectively extending across the first and second fins, and a gate isolation plug between a longitudinal end of the first gate structure and a longitudinal end of the second gate structure. The gate isolation plug comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer has an upper portion and a lower portion below the upper portion. The upper portion has a thickness smaller than a thickness of the lower portion of the first dielectric layer.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

Abstract: A semiconductor device includes a first memory array, a first bit line, a second memory array, a second bit line, a first conductive line and a first control circuit. The first bit line crosses over and is coupled to the first memory array, and extends along a first direction. The second bit line crosses over the second memory array, and is coupled to the first bit line. The first conductive line crosses over the second memory array and a part of the first memory array, and is configured to operate as a part of a first capacitor. The first control circuit is configured to couple the first conductive line to the second bit line when the first memory array is written.

Abstract: A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a memory cell connected to a bit line, and a biasing circuit configured to output a first bias voltage and a second bias voltage, the first bias voltage generated based on a threshold voltage of a p-type transistor, and the second bias voltage generated based on a threshold voltage of an n-type transistor. The semiconductor device includes a step-down circuit connected to the bit line and configured to receive the first and second bias voltages, the step-down circuit configured to output an output voltage to charge the bit line based on the first and second bias voltages.

Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the source electrode and the drain electrode are arranged on one side of the gate insulating layer, wherein the gate insulating layer includes multilayer oxide films stacked on each other and at least one interface layer between the multilayer oxide films, and the material of the at least one interface layer is different from the material of the oxide films.

Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.

Abstract: A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

Abstract: A method includes forming a static random access memory (SRAM) array comprising a plurality of SRAM cells, at least one of the SRAM cells comprising first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors; forming a first front-side metal layer above the SRAM array, the first front-side metal layer comprising a first power supply voltage line and a bit-line, the first power supply voltage line electrically coupled to the first and second pull-up transistors, and the bit-line electrically coupled to the first pass-gate transistor; forming a back-side butt contact extending from a back-side of a gate structure of the first pull-up transistor to a back-side of a source/drain region of the second pull-up transistor from a cross sectional view.