Abstract: Multiple processors are connected to form a multiprocessor system having interprocessor communicating capability. In the face of a power-fail signal, indicating that possible power loss is imminent, a processor will proceed through a shut-down procedure to save the present operating state so that when power is re-applied the processor can continue from the operating state it left when power was lost. The shut-down procedure concludes with the processor broadcasting messages to all other processors that it is undergoing a power-fail shut-down which is noted by the other processors to later cause them to enter a cautious mode of operation so as to not exclude the processor in any system configuration involving agreement of all processors by reason of the processor's loss of power.

Abstract: A method and digital circuit for indicating whether the frequencies of two clocks are within a predetermined range of each other, wherein a first pattern of alternating binary one's and zero's is created using the active edge of the first clock; first and second sampled patterns are generated by sampling the first pattern with respective first and second edges of the second clock; and a first acceptance signal is asserted if either the first or second sampled pattern has alternating binary one's and zero's. A second acceptance signal is asserted as above but interchanging the two clock signals. A near-frequency signal is generated when both acceptance signals are asserted. A clock error signal is the inversion of the near-frequency signal.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: A multiprocessor system is configured so that each of the central processing units (CPUs) of the system have accessed at least portions of the memory of each other CPU. Interprocessor messaging is conducted by a CPU writing to, or reading from, the memory of another CPU of the system.

Abstract: A method and apparatus for detecting and tolerating situations in which one or more processors in a multi-processor system cannot participate in timer-driven or timer-triggered protocols or event sequences. The multi-processor system includes multiple processors each having a respective memory. These processors are coupled by an inter-processor communication network (preferably consisting of redundant paths).Processors are suspected of having failed (ceased operations) outright or having a failed timer mechanism when other processors detect the absence of periodic "IamAlive" messages from other processors. When this happens, all of the processors in the system are subjected to a series of stages in which they repeatedly broadcast their status and their connectivity to each other. During the first such stage, according to the present invention, a processor will not assert its ability to participate unless its timer mechanism is working.

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

Abstract: An improved method and apparatus for creating a context-sensitive pathsend in a asynchronous data packet network of the kind used typically in on-line transaction processing where a particular receiving server in a server pool must communicate with a particular originating client. By piggybacking messages and employing run-time binding to create a logical connection between the server and client, the present invention achieves a dramatic improvement in processing data packets and minimizing system resources. In a preferred embodiment the invention is backwardly compatible with existing context-free applications.

Abstract: An apparatus and protocol to determine the group of processors that will survive communications faults and/or timed-event failures in a multiprocessor system. The processors each have a respective memory, and the processors are coupled by means of an inter-processor communication network. The processors detect that the set of processors with which they can communicate has changed. They can choose to either halt or continue operations based on minimizing the likelihood that disconnected groups of processors will continue to operate as independent systems. The processors construct a connectivity matrix on the initiation of a regroup operation. The connectivity information is used to ensure that all the processors in the final group that survives can communicate with all other processors in the group. One or more processors may halt to achieve this characteristic.

Abstract: Disclosed is method for aligning and mounting electrical components, such as packaged integrated circuits, to a printed circuit board. During an alignment phase, a sample component is attached to a stand-in circuit board at a component site. A base plate, having alignment elements, is then fitted to the board proximate the attached sample component. Next, a chuck is mounted to the sample component, and an alignment plate positioned to engage the alignment elements of the base plate, and affixed to the chuck, forming a chuck assembly that is aligned to the base plate and registered to the component site of the circuit board. During a production phase, the base plate is placed on a printed circuit board at a location substantially identical to that on the stand-in printed circuit board. A chuck assembly, configured substantially identical to that formed during the alignment phase, and carrying a component to be mounted, is attached to the base plate so that the alignment plate engages the alignment elements.

Abstract: In a distributed network system, resilient virtual fault tolerant service sessions are conducted between a host application program and a telnet client user over an end-to-end link including a telnet server, a messaging protocol process, a network driver, and a communication link. The telnet server establishes a tty type structure in response to a service request from a telnet user/client. This invention includes a service control block which controls the establishment of a tty and associated request control blocks and buffers for processing I/O requests. The session is functionally partitioned into an upper half session involving the host application program and the telnet server, and a lower half session involving the remainder of the network components leading to the telnet client.

Abstract: A transaction checking system for improving the level of software fault tolerance in a distributed processing environment by aiding the client computer system in the recovery process. The transaction checker system enables the client computer system to determine, after a system failure, the state of the last transaction so that the client computer system can begin the recovery process.

Abstract: A method and apparatus for blind alignment of electronic circuit boards. A receptacle with two vertical flanges and one horizontal flange is positioned relative to an electrical connection. A circuit board having a notch on a leading edge is proximally positioned to the receptacle. As the notched edge is moved toward the receptacle, the flanges guide the board into a registered position relative to the electrical connection. The method and apparatus may be used in any number of alignment situations including those as disparate as robotic assembly operations and assembly by untrained consumers and end-users.

Abstract: A method of encoding data and commands as N-bit words includes using a first portion of the word to identify whether the word carries data or a command. In the case of a command, the command is in a second portion of the word. In the case of data, a part of the data is contained in the second portion of the word, while the remaining part of the data is encoded in the first portion of the word.

Abstract: A DC power distribution system can be configured to utilize a variable number of AC power distribution units. Installation of a converter unit in place of a PDU and resetting of associated switches permits inexpensive and rapid reconfiguration of the system without interrupting power supply to current receiving units. Techniques such as mechanical keying and sense switches minimize the possibility of human error in the reconfiguring operation.

Abstract: A method and apparatus for transporting IDL-defined data structures to and from a format convenient for transport between two computers are disclosed. The data structures is originally described in a string. The string description is converted to a different format containing additional information about the alignment and size of the data structure. An application in the sending computer removes the alignment from the data structure and stores the data structure in a buffer. The data structure is stored in the output buffer in a predetermined format that is based upon the type of the data structure. The buffer is then transmitted to a data file or to the memory of the receiving computer. The receiving computer extracts the data structure from the buffer based upon the predetermined format. The data structure is realigned and stored in the memory of the second computer.

Abstract: An apparatus and method for getting descriptors to data and passing the descriptors among data sources and sinks, thereby avoiding copying the data among the data sources and sinks. The data source/sink which consumes the data actual initiates the copying of the actual data itself, using global pointers to the data in the descriptors.

Abstract: A highly reliable computer memory storage system that is divided into subsystems, each of which is provided in triplicate: a primary subsystem, a backup subsystem and a spare subsystem. Upon detection of a non-recoverable failure in a primary subsystem, the backup subsystem substantially immediately assumes the tasks of the primary subsystem while the spare subsystem is integrated into the operation of the computer memory storage system. The triple replication of all subsystems and mechanisms for detecting failures in at least the primary and secondary subsystems provides an overall memory system which is highly reliable and substantially never requires servicing. In an alternative embodiment, three subsystems can share a load equally, for example a cooling or power supply load requirement.

Abstract: A method and apparatus are disclosed for improving public key encryption and decryption schemes that employ a composite number formed from three or more distinct primes. The encryption or decryption tasks may be broken down into sub-tasks to obtain encrypted or decrypted sub-parts that are then combined using a form of the Chinese Remainder Theorem to obtain the encrypted or decrypted value. A parallel encryption/decryption architecture is disclosed to take advantage of the inventive method.

Abstract: A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.