Abstract: A computing system includes a pair of central processor units structured to operate in substantial synchronism to each execute the same instruction at substantially the same moment in time of identical instruction streams to achieve a logical central processor unit with fail-functional operation. One of the central processor units includes a pair of processors that execute, instruction by instruction, the instruction stream with checking for fail-fast operation. The other central processor unit includes only a single processor element. The system achieves a low cost fail-functional architecture.

Abstract: A bracket (28) secures a header (12) to a PWB (22) and includes a face plate (32) having an opening (34) sized to receive a portion (33) of the header. The face plate, and header therewith, is secured to the PWB by mounting tabs (44) secured to and extending from the face plate. Each mounting tab is relatively thin and has its narrow-width peripheral edge portion (56) adjacent to the surface (24) of the PWB. The edge portion has an opening (54) sized to accept a rivet (62) to affix the bracket to the PWB. The edge portion contacts a ground pad (66) on the PWB to provide grounding of the PWB through the bracket. The bracket includes centering tabs (48) which engage the edges (62) of the chassis openings (10) to properly position the header in the opening.

Abstract: A supply voltage monitor for providing an indication of a supply voltage level considered safe for electronic circuit operation includes a supervisory or guard circuit that blocks the output of the monitor in favor of a secondary output for those periods of time when the monitor is considered to not be able of providing a valid reflection of supply voltage status.

Abstract: A cache is distributed among processors in a multiple processor system with no shared memory to maintain the cached data. Each processor maintains a cache which identifies the opened files being cached, the blocks of each file which are cached and the state of caching for each file. The state of each opened file is one of "no-caching", "read-caching" and "read/write caching". So long as only one processor opens a file, and opens it for read/write access, that processor is allowed to do read/write caching on the file. When a processor opens a file for read access, that processor is allowed to do read caching, unless another processor has the file open for read/write access. After the last processor having read/write access to a file closes the file, the disk system upgrades the cache state for the file.

Abstract: An improved recovery method utilizes sequence numbers to order log records and reduce the excess compensating actions due to a failure during recovery. Next undo records are written to the log after a preset number of compensating actions which include the sequence number of the record currently being scanned. After a failure, all records between the next undo record and the record having the sequence number included in the next undo record are ignored during when the log is scanned backwards.

Abstract: A computing system develops time/date values by using a free-running counter to measure and accumulate increments of time. The increments of time are converted from the resolution of the free-running counter to that used for the time and date values by dividing by a conversion variable and then used to update the time/date value. The accuracy of the time/date value is monitored by periodically comparing the rate of the free-running counter to the rate of a more accurate, external clock. The ratio of these two rates is used to adjust the conversion variable. The conversion variable reflects any differences between (1) the rate of change of the increments of time used for developing the time/data value and (2) the external clock. Its use here, therefore, will operate to either slow down or speed up the rate of change of the time/date value so that it more closely tracks the external clock.

Abstract: An system and method for creating applications having look and feel providing dynamically extensible languages for describing application look and feel. Engines are provided for executing programs written in the languages, and methods for extending the languages by creating new language operators are also provided. Methods for joining modules of functionality to new operators allow display of, and interaction with, functionality to be expressed in the extensible languages. The engines and languages permit language operators and functionality modules to be dynamically loaded.

Abstract: A method and system for preparing a suite of test scripts for testing a proposed network management application. The proposed network management application, termed a subsystem control facility (SCF), is first defined as a set of requirements with the aid of a developmental tool incorporating a subsystem knowledgebase and a test generation knowledgebase. The subsystem knowledgebase contains the rules governing the operation of a given network and a library of permitted commands, objects, attributes, modifiers and other data. The test generation knowledgebase includes information relating to those commands and object specific to the proposed subsystem control facility set of requirements. A user interface coupled to the knowledgebases permits the selection of types of tests and specific commands and objects to be tested.

Abstract: A data processing system for transferring data is provided. This system includes central processing units (CPUs 20, 22, 24 and 26) and storage units (30 and 32 with 100-105 and 110-115) which are interconnected by a network (10). The CPUs (20, 22, 24 and 26) include a request process (133) and a storage process (130). The storage process (130) controls access to the storage unit (30 with 100-105 and 110-115). Software routines (220) are used to provide direct access to the storage unit (30 with 100-105 and 110-115) by the request CPU (22). The request CPU (20) is the CPU containing the request process (133). A virtual memory address for a buffer (160) of the request CPU (22) is created in the request CPU (22). The virtual memory address along with a storage unit access request are sent to the CPU (20) containing the storage process (130). A work request including the virtual memory address to sent from the storage process (130) to the storage unit (30 with 100-105 and 110-115).

Abstract: An apparatus and method, using an inter-processor lock to control access to inter-process relationship data structures in the memory of each processor in a multiprocessor system. The apparatus and method insure that each inter-process relationship is modified in the same sequence on each processor. The apparatus and method also insure that an inter-process relationship is maintained in a consistent state in the face of failure of any of the processors.

Abstract: An apparatus and method for getting descriptors to data and passing the descriptors among data sources and sinks, thereby avoiding copying the data among the data sources and sinks. The data source/sink which consumes the data actual initiates the copying of the actual data itself, using global pointers to the data in the descriptors.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: An effective connector mechanism is described which allows modules (10, 12) to be easily and reliably connected and disconnected. This connector mechanism includes a coordinated arrangement of guide plates (28, 54) featuring mating guide rails (56) and U-shaped channels (32) along with matched sets of tapered pins (38, 40) with tapered slots (58, 59). The pins and slots are "tapered" in the sense that the pins have a slanted surface (52) on the shank (44) directly underneath the head (42) which urges the guide plate surface adjoining the slot downward after engagement and the slots have a slanted edge (66) at their closed end (62) which maintains contact with the pin after engagement. When mated together, the rails, U-shaped channels, pins and slots lock the modules into engagement in virtually every direction.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A database management system (DBMS) provided with a multi-dimensional improved indexed accessing capability using keyed index searching. Individual search keys are constructed from general expression statements created in the DBMS compiler from search queries supplied to the DBMS. Each key column represents another dimension, and both ranges and IN lists can be specified in the search query and used as the predicate values in multiple columns. Missing predicate values in the search query are interpreted as a specification of the minimum and maximum values for the associated search key column. During compile time, the DBMS compiler produces general expressions to be used by the DBMS executor during run time to create the search keys. The DBMS compiler evaluates search queries by associating predicates with clusters and disjunct numbers assigned to each individual disjunct in the search query expression.

Abstract: A fault tolerant network interface is achieved by providing primary and alternate network controllers, dual transceivers, dual cables and dual connectors. This fault tolerant interface is driven by a logical device driver which controls the physical device drivers for the primary and alternate network controllers. The logical device driver causes periodically polling messages to be sent between the primary and alternate network controllers to determine if a fault has occurred in either of these network controllers. Faults detected are logged and error recovery actions are provided according to the nature of the faults detected. If the primary network controller is found to be faulty, the secondary network controller will assume the physical address of the primary network controller and provides the services of the primary network controller while the primary network controller is effectively removed from the network.

Abstract: First and second data processing systems located at first and second sites are configured with the first data processing system having a primary memory unit at the first site and a mirror memory unit at the second site with the first and second sites coupled by a single-mode optical fiber. Fiber optic switches at the first and second sites can be reconfigured to coupled the mirror disc to the second data processing system with minimal delay.

Abstract: A method, system, apparatus, and program for translating one computer language to another using doubly-rooted tree data structures. A doubly-rooted tree is the combination of two sets of hierarchically related objects sharing a common set of leaves. An N-rooted tree is also described. When a doubly-rooted tree is constructed in the specified manner and then translated to a second doubly-rooted tree, source language code is transformed into target language code. In addition, the translation preserves preprocessor characteristics of the source language code including macros, conditionally compiled regions of code, source inclusion statements, and comments.

Abstract: First and second banks of control stores are used to store microinstructions. Each bank contains three control stores: A horizontal control store, a vertical control store, and a jump control store. The horizontal control store contains the rank four microcode; the vertical control store contains the rank three microcode; and the jump control store contains the same microcode as the vertical control store but is used on conditional jump microoperations. This allows simultaneous accessing of different microinstructions using a single address incrementer. The control store banks are accessed in an overlapping manner so that upon each clock cycle one bank is loading the rank 3 and rank 4 registers. The sequencer according to the present invention includes a return address stack for returning from subroutine calls and trap routines.

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.