Abstract: A power switching circuit module includes two power rails coupling independent power supplies to the input of a DC controller and test circuits to detect latent faults in power mixing devices included in the circuit.

Abstract: A processor system comprising a number of data handling units interconnected by a system bus operates according to a novel protocol wherein one of the number of data handling units issues a buss request signal together with a separate arbitration signal uniquely identifying the data handling unit requesting access to the system bus. Distributed priority determination logic, located in each data handling unit, allows each data handling unit requesting bus access at the same moment in time to independently and unilaterally ascertain who has access. The bus request signal remains asserted to hold off any additional requests for bus access until all data handling units first requesting access have been serviced.

Abstract: To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A modular bus routing system incorporates segments of a plurality of parallel buses in a substrate on which device connectors are strategically located. Each end of each bus segment is coupled to a connector mounted on the substrate and interconnection between bus segments on different substrates is afforded by a flexible cable containing bus conductors of controlled length and electrical characteristics. A plurality of personality cards provide several different types of bus segment interconnection so that different segments can be terminated, or jumpered to other segments on the substrate. By selecting different personality cards, the plurality of bus segments on a given substrate can be configured as a single serially connected bus, two, four or eight buses. The system affords wide flexibility for computer systems using host initiators and mass storage devices to provide a highly configurable computer system using such elements.

Abstract: An apparatus and method of correcting parity errors in a fault tolerant computer system. Data and associated parity are checked in parallel with use of the data by an ALU. Upon detection of an error, a controller causes the ALU to pass the input data unchanged and associates a correct parity with the input data. The correct parity generation is done in parallel with ALU processing to permit rapid reassociation of data and its correct parity. The reassociated data is returned to the ALU for processing.

Abstract: A boundary scan bus error reporting circuitry loads an unused sentinel bit pattern into the boundary scan instruction register in a conventional error reporting boundary scan test system. The unused sentinel bit pattern signifies that a fault exists somewhere upstream of the instruction register in the boundary scan circuitry associated with a specific integrated circuit. The special sentinel pattern is loaded into the instruction register in response to an illegal instruction control signal generated by an instruction decoder coupled to the instruction latch in the boundary scan architecture.

Abstract: Disclosed is apparatus for aligning and mounting electrical components, such as packaged integrated circuits, to a printed circuit board. During an alignment phase, a sample component is attached to a stand-in circuit board at a component site. A base plate, having alignment elements, is then fitted to the board proximate the attached sample component. Next, a chuck is mounted to the sample component, and an alignment plate positioned to engage the alignment elements of the base plate, and affixed to the chuck, forming a chuck assembly that is aligned to the base plate and registered to the component site of the circuit board. During the production phase the base plate is placed on a printed circuit board at a location substantially identical to that on the stand-in printed circuit board.

Abstract: A multi-processor system having mirrored memory units accessible by either processor. The term "mirrored memory" in the context of the present invention describes the ability of each of the processors to directly READ and WRITE the contents of its own local random access memory (RAM) unit and in the local RAM unit of the other, remote processor. The mirrored memory of the present invention comprises two units of triple-ported RAM, each unit interconnected by a pair of interprocessor busses to the corresponding triple-ported RAM of the remote processor. "Triple-porting" describes the three input/output ports available for accessing a RAM unit. An internal port is used by a processor to access its local RAM, while the other two ports are provided so that the same RAM can be accessed by the remote processor through the paired interprocessor busses. Each processor may READ or WRITE its own local RAM, the remote processor's RAM, or both RAM's during a single operation.

Abstract: A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.

Abstract: A power mixing apparatus for mixing current from a first and a second power rail includes a first enabling circuit to provide a first enabling signal, a second enabling circuit to provide a second enabling signal, a first inrush limiter to output a first current in response to the first enabling signal, a second inrush limiter to output a second current in response to the second enabling signal, a first open-circuiting circuit to decouple the first enabling circuit from the first inrush limiter when the first open-circuiting circuit is open-circuited, a second open-circuiting circuit to decouple the second enabling circuit from the second inrush limiter when the second open-circuiting circuit is open-circuited, a first isolation circuit to isolate the first inrush limiter from the second current, a second isolation circuit to isolate the second inrush limiter from the first current, and a direct-current converter to convert the first and the second current in response to the first enabling signal and in respo

Abstract: A fault tolerant computer system having a plurality of processor modules having independent clocks for processing an instruction stream, global memory accessible by all of the processor modules, and a local memory configured within each processor module and clocked synchronously therewith. The local memory is periodically refreshed between accesses to the local memory by the processor. Warning signals indicating a potential access to the local memory are provided to a refresh controller and the local memory is refreshed or the refresh is aborted depending upon the number of clock cycles available before a local memory access occurs. A speculative refresh may be stalled until a processor instruction is decoded to determine whether a local memory access is requested or not.

Abstract: A master clock signal, used to operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or that communicate such signals to a destination external to the integrated circuit.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A detachable dolly for moving heavy electronic equipment employs a mounting bracket and a wheel assembly, the mounting bracket having a support plate and a mating flange. The mounting bracket is secured to the equipment by the support plate, having at least one lifting dowel, and at least one mounting bolt. The wheel assembly has a wheel mounted within a wheel bracket and a rotation adjustment mechanism for raising and lowering the wheel and is detachably engaged with the mating flange on the mounting bracket by the use of a mating member. The mating member is movably coupled with the adjustment assembly such that when the mating member is engaged with the mating flange, rotation of the adjustment assembly serves to vertically raise or lower the equipment.

Abstract: A clock synchronization system includes a clock generator for producing first and second system clock signals that are each received by corresponding ones of a pair of integrated circuits from which the integrated circuits each produce secondary clock signals. The clock system includes synchronizing circuitry that receives the secondary clock signals to determine the phase difference between them, and delaying one of the system clock signals, relative to the other, in a manner that results in the state transitions of the secondary clock signals occur within a period of time of each other.

Abstract: A data communication system embodying an apparatus and a method provides simultaneous paths between a plurality of transmit ports and a plurality of receive ports for transmitting therebetween data identifying their destination receive ports. Such data are signals which are constructed in accordance with a standard serial protocol for frame element communication, such as HDLC (High-level Data Link Control). The system is assembled in a chassis containing a backplane and multiple cards having transmit and receive ports through which the cards couple the backplane.

Abstract: A scannable logic unit includes one or more storage registers that maintain copies of data communicated from the scannable unit to registers in a nonscannable unit. When the scannable unit is subjected to a scan test, the registers will contain state information respecting that transfer to the nonscannable unit. When the scannable and nonscannable units are placed in a run condition, the registers supply to the nonscannable unit state information for continuing operation.

Abstract: A computing system, having an input/output bus for communicating data thereon, is connected to a network by a pair of network controller devices. Each of the network controller devices, in turn, connect to a corresponding one of a pair of multi-ported network repeater elements which are, in turn, connected to one another by a pair of network links. At least one workstation is connected to each of the network repeaters. One of the network controllers is initially selected as a primary data communicating path from the computing system to the network. The network controllers periodically transmit messages to one another, and if receipt of those messages by the primary network controller is noted, the selection of the primary controller will be switched to the other.

Abstract: A fault-tolerant control and monitoring system for fan assemblies used in electronic equipment. The fan control and monitoring system of the present invention reduces the probability of high temperature damage due to power failure by using a power mixing circuit that provides redundant power to the fans. The system includes means for detecting faults in the power mixing circuit. The system of the present invention further includes means for measuring the exact speed of the fans, as well as means for finer control of fan speed. Physical presence of fan unit is detected without additional pin requirements.