Abstract: A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network is configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each successive transfer between neighboring nodes. The buffer locations are managed so that they can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.

Abstract: A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network may be configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each successive transfer between neighboring nodes. The buffer locations are managed so that a node can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.

Abstract: A method for forming multiple metallization layers on a semiconductor wafer comprises applying insulating polyimide layers between adjacent metallization layers. Vertical interconnect holes are formed through the polyimide insulating layers using a positive photoresist mask. The vertical interconnect holes are etched using a fluorocarbon- or fluorosilicon-oxygen plasma under power and temperature conditions which provide for selectively etching the polyimide relative to the photoresist. By initially forming the plasma etch at high power conditions which reduce the selectivity for the polyimide, the upper portion of the vertical interconnect hole walls may be flared to reduce problems with step metallization. The remaining portion of the plasma etch, however, is performed under conditions which are more highly selective for the polyimide which provides for better dimensional control and eliminates formation of a contaminating layer at the bottom of the vertical interconnect hole.

Abstract: A structural support and thin panel assembly wherein the longitudinal axis of the structural support is attached perpendicular to the thin panel comprising a structural member, a thin panel, a female member attached to the structural member and a fastening means removably attaching the female member to the thin panel.

Abstract: The disclosure relates to the use of a flip flop or the like to provide additional protection against the destruction of data located in microprocessor system support circuits.

Abstract: The present disclosure relates to a communications method for communicating data over a data channel that comprises two unidirectional communication lines. A protocol which is set of predetermined control characters is used by the communications method and the protocol is used for transferring data between communicating devices. The communications method combines acknowledgements which are control characters of the protocol transmitted in between messages, piggy-backing which is the combining of control characters of the protocol and data messages, and hold-offs with long time outs which cause the devices to enter a standby idle mode waiting for a responsive control character of the protocol. The communications system and method combines these features so as to permit improved efficient flow control of data information between the communicating devices.

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules.The multiprocessor system includes a distributed power supply system which insures non-stop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. A power interlock system and a method are provided for protection against data corruption.

Abstract: Disclosed is a base drive circuit that provides a base drive current particularly adapted to switch a switching power transistor ON and OFF quickly. The base drive current includes a variable AC impedance device that responds to a control pulse to form a base drive having (a) an initial forward base drive peak that drives the switching power transistor toward deep saturation momentarily, followed by (b) an intermediate drive current of lower magnitude, sufficient to keep a high-power transistor at or near saturation, and (c) a high-amplitude reverse drive current for high-speed turn-off of the transistor.

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored and return to a desired line after a delayed call.

Abstract: The disclosure relates to a re-vectoring circuit of a microprocessor system wherein pending interrupts are serviced without unnecessary microprocessor state store and restore operations associated with a return-from-interrupt instruction. At the conclusion of an interrupt service routine, an indirect jump instruction is executed through the same address location of an interrupt vector that the microprocessor indirectly jumped through when the microprocessor was initially interrupted. However, the indirect address is modified, that is, re-vectored to an indirect address within a predetermined address vector depending upon the type of a pending interrupt. The re-vectoring circuit recognizes the indirect jump address and then senses a pending interrupt if there is a pending interrupt. The re-vectoring circuit modifies the indirect address such that a jump occurs to the highest priority pending interrupt service routine.

Abstract: Electronic system grounding includes two system grounding paths for card caged electronic modules, with a first grounding path through the card cage and a second grounding path through the system power supply. The two system grounding paths are used to minimize noise and reduce unwanted induced superimposed transient voltage levels.

Abstract: Method and hardware associated with an arithmetic logic unit (ALU) in a central processing unit of a data processor provides for testing the inputs to the ALU to see if logical AND is zero or the two inputs are equal while allowing the ALU to perform another function at the time these tests are made.

Abstract: The present invention relates to a system for controlling multiple communications lines, so that a computer system can operate with a single component failure. Two processors are used to control two communications controllers and each of the controllers control up to 15 line controllers. Each line controller has two ports and each port is connected to a communications controller thereby providing two communications paths to each processor. Redundant power supplies are also used to provide single failure fault-tolerance. A downloadable microprocessor board is provided in combination with, but separate from, an interface board that is designed to meet various communication format specifications and the line controller comprises the two boards.

Abstract: A connection system for host equipment is disclosed. The system includes a plug-in electronic module and a power supply cable for plug-in connection to said module. The host equipment includes a housing for the module which effectively precludes access to the module except at one exterior end thereof. An end plate at an exterior end of the module includes a handle facilitating removal of the module from the housing. The end plate further comprises a power supply cable jack for mating with a plug of the power supply cable. The jack and the plug are so located and adapted to render ineffective the handle when the plug is mated with the jack, thereby requiring the service personnel to remove the power supply plug from the jack before removing the module from the housing.

Abstract: An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction. Subsequent lines of microcode for that macroinstruction are fetched from a main control store.

Abstract: Hardware for performing microcode branching in a pipeline central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit lines of microcode which are in the pipeline when a branch has been sensed. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupling loading and pushing to accommodate the two branching speeds. The microcode can specify loading the return address stack with a literal or register value to allow vectored branching and return to a desired line after a delayed call.

Abstract: A switching power supply uses constant current sources, switching transistors and current coupled transformers for switching current through the switching power supply. The switching current is proportional to the current of the constant current sources. The use of constant currents to drive output transistors of the switching power supply improves the efficiency of the switching power supply and desensitizes the switching power supply to variations in unregulated power sources.

Abstract: An input/output system for a processor of the kind in which a processor module has a central processing unit, a memory, an input/output channel, and a plurality of device controllers for controlling the transfer of data between the processor module and the peripheral devices includes a star poll connection in which each device controller is provided with a signalling means for signalling its identity in response to a poll operation, independently of other similarly connected device controllers such that any number of device controllers can be failed or powered off without affecting the polling of the other device controllers. The data lines in an input/output bus are used both to transmit data and to transmit signals to reduce the total number of lines needed to connect the device controllers to the channel in the star poll connection. The system is a fault tolerant system which includes an enable bit in the port of each device controller.

Abstract: A datapath system and protocol is disclosed in which data is transferred between a computer memory and one or more peripheral devices through device controllers, each of which includes a buffer, through periodic connection of the device controller to the channel. The system and protocol are structured to permit multiple device controllers to cooperatively interact on a single channel, without direct communication between device controllers. Each device controller monitors the level of stress on its buffer and at appropriate times presents a reconnect request to the channel, together with indica for permitting the channel to determine the priority of a particular request relative to other reconnect requests. The times at which a reconnect signal should be presented are determined by monitoring the level of information storage in the buffer and relating that level to a threshold level; both overfilling and overemptying are prevented.

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus.The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs.