Abstract: A system for preventing voltage drops when a load circuit is connected and preventing arcing when a load is disconnected from an energized bus includes a current limit device and low impedance shunt that bypasses the current limit device when activated. The system activates the low impedance shunt only after a load capacitance is charged when the load is connected and deactivates the low impedance shunt prior to disconnecting the load.

Abstract: A circuit for controlling data transfer handshake protocol so that certain protocol events may occur prior to or simultaneously with the completion of a proceeding protocol event, and the ultimate results of the pending protocol event may be determined at a later time. In one embodiment of the invention a CPU operates to transfer data (either receive or send) between itself and an I/O channel every five processor clock cycles. At the beginning of each set of five clock cycles the CPU places data on the data bus and generates a transfer request (CPU-XFR) signal whenever it receives a data accepted (DATA-ACC) signal indicating that a previous data transfer has occurred. The CPU-XFR signal is generated regardless of whether or not the previous data transfer is complete at the time. The data transfer normally is completed one clock cycle after the CPU-XFR signal is generated, and at that time a transfer complete signal is generated.

Abstract: A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

Abstract: A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was correctly predicted. If the branch was not correctly predicted, the writes and stores of instructions in the family the precede the branch instruction are completed and those instructions are retired. However, the writes and stores of the instructions in the family following the branch instruction are inhibited.

Abstract: A one out of N checking circuit for determining whether exactly one of N signal lines is active at any given time. The circuit includes a hierarchal structure of nodes which pairs the N signal lines together in a series of steps. Each node includes a par of output signal lines. The first signal line carries a signal representing whether an active signal line was "seen." The second signal line carries a signal representing whether an error has occurred, i.e. multiple active lines were seen. After each step, the number of signal lines is reduced by one-half until only two signal lines remain. At that point the two signal lines are compared and a final error signal is transmitted.

Abstract: An integrated circuit chip carries a number of electronic circuits, at least one of which includes, in its output stage, a control device that responds to a reference signal to adjust the output current-handling capability of the electronic circuit, thereby regulating the signal propagation delay exhibited by the electronic circuit. The reference circuit is generated by a digital-to-analog circuit that is also formed on the chip. The digital-to-analog circuit is coupled to a number of contact elements disposed on an outer surface of the package containing the integrated circuit chip that can be selectively interconnected to a DC voltage to choose the value of the reference signal.

Abstract: A multiple power supply sensor for protecting shared processor buses in a multiprocessor system. In the case that a power failure or power supply malfunction occurs in one of the processors of the system, at least one of the shared processor buses will be isolated from the malfunctioning processor. As a result, data on that bus is not corrupted by the manfunctioning processor. The isolation is accomplished by independent sensor circuits present in each processor for each bus.

Abstract: The present invention is directed to a self-calibrating clock synchronization system that receives a periodic, digital clock signal as a reference and generates therefrom a system clock signal that dynamically tracks and is synchronized to the reference clock. The invention utilizes state machine controlled selection circuitry that comprises a plurality of predetermined delays tapped to produce a number of phase-related clock signals, and multiplexing circuitry, for selecting one of the plurality of clock signals as the system clock. A comparator compares the selected clock signal and the reference clock to determine which leads or lags the other. In response to the comparison, selection, from the plurality of clock signals, of a system clock that most clearly matches the reference signal is made.

Abstract: Encoding and decoding circuits are described for functioning as both a time and voltage based transmission system. Multiple binary inputs can be transmitted and received on a single I/O pin by encoder and decoder circuits using high speed emitter coupled-like logic.

Abstract: A fixed entry-point map to produce an entry point address of a first micro-instruction for a particular macro-instruction. That address is then incremented by a fixed number to produce the second, third, etc. micro-instructions for that macro-instruction. In a first embodiment, after a fixed number of these address skips, the addresses are incremented by 1 so that successive micro-instructions are in adjacent address locations. In a second embodiment, the number of skips is variable.

Abstract: In a data processing system, a multiplication operation is immediately followed by a redundant multiplication operation, using the same, albeit altered, operands, to check the initial result. The initial result is immediately available for use, but the check is not performed until some time later. The original operands are altered for the redundant multiplication operation by shifting one operand 1 bit, and swapping them before multiplication.

Abstract: A method and mechanism operate for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.

Abstract: A balanced three phase AC power supply for a computer system having unbalanced, variable DC loads. AC to DC converters utilize high power factor correction circuitry to impose a sinusoidal current loading waveshape substantially in phase with the AC voltage. Each AC to DC converter outputs equal DC voltages maintaining a balanced loading on the AC power source. The design and organization of the power supply components make the supply fault tolerant when one phase of AC power or one AC to DC converter is lost due to malfunction or servicing.

Abstract: In a data processing system, a device controller, configured to control data transfers between a processor unit and a peripheral device on an input/output bus, is provided with apparatus that permits a data transfer cycle to continue until all data has been transferred, or to allow for interruption of the data transfer cycle by another device controller requesting access to the input/output via a request signal. During a data transfer cycle the apparatus resonds to detection of the request signal to interrupt the data transfer cycle after a predetermined number of data words are transferred, permitting access to the input/output bus for other of the device controllers. In absence of the request signal, the apparatus permits the data transfer to continue until all data has been transferred between the peripheral device and the processor unit.

Abstract: An apparatus for testing cables, cable connections associated with devices and devices in a daisy chain configuration. Cable malfunctions and cable connection malfunctions can be isolated down to a single device in a daisy chain system by looping back the data bus to the control bus or vice versa. A signal is then sent out on the first bus and received back on the second bus. If a cable malfunction is present, the signal received will not be the same as the signal transmitted.

Abstract: A method and apparatus for changing the key in a cryptographic system or device are disclosed. A memory contains three storage areas for pending, active, and retired keys. New keys are loaded into the pending storage area. The key is changed by shifting the pending key into the active storage area and shifting the active key into the retired area for use by applications which have not been made aware of the key change. When an application presents a retired key, use of the retired key is allowed and the new key is returned to the application.

Abstract: A system interconnects electronic modules with one another, to a power supply and to signal lines through a printed circuit board. The modules are electrically connected to traces on the printed circuit board using blind mateable connectors. EMI shielding plates are mounted to the circuit board at the I/O connectors for the external cables. Guide elements, such as pin and socket guides and printed circuit board edge guides, are mounted to the circuit board to guide the blind mateable connectors. The syustem eliminates the numerous cables which would otherwise be required. The printed circuit board is mounted within the system housing and acts as an air duct barrier to aid proper air circulation. The circuit board also acts as a structured element helping to stabilize the housing and various module supports and serves as a mounting structure for various elements, such as cooling fans.

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. Memory references. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references by the multiple CPUs are voted by each of the memory modules. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.

Abstract: Encoding and decoding circuits, utilizing high speed ECL-like logic, simultaneously transmit and receive multiple binary signals via a single I/O pin.

Abstract: A facsimile transmission system is used to transmit documents over telephone lines using an electronic mail system, which may be a localized system or a distributed electronic mail system. Transmission is initiated by the sending facsimile machine transmitting a mark sense cover sheet, which has a mark sense identifier printed on it, to a facsimile controller. The controller checks for the presence of the mark sense identifier and if present, the controller reads the identifying information and destination address coded thereon. The controller then transmits the identifying information and destination address and the subsequently received document facsimile data to the electronic mail system in digital form, for retransmission back through the same or a different controller to one or more receiving facsimile machines.