Abstract: A fault tolerant computing facility is disclosed. The facility includes a housing array for containing a plurality of hardware element modules such as disk drives, a plurality of modularized power supplies and plural power distribution modules, each being connected to a separate source of primary facility power. Each module is self aligning and blind-mateable with the housing and may be installed and removed without tools, without disturbing the electrical cabling within the cabinet, and automatically by a maintenance robot. The logical identity of each module is established by programming at a control panel and by corresponding physical location of installation of each module within the housing array.

Abstract: An overlapped control store including a pair of memory elements, with each element in the pair storing a complete instruction set and with instructions from the elements accessed on alternate clock cycles. A mux, controlled by a control field in each instruction, is adapted to provide either a PC address or a target address to the control store. Unrestricted branches are facilitated because every instruction in the instruction set is included in both memory elements.

Abstract: A system for compensating for varying attenuation of an uplink signal from a local node to a satellite. The system monitors two beacon signals and the local downlink signal to determine fade. An error signal, indicating the uplink fade, is generated and utilized to adjust the gain of the uplink transmitter to compensate for the fade.

Abstract: An improved fan, for mounting adjacent an opening in a mounting plate, includes blades rotatable about an axis and within a cylindrical housing. The fan blades move air through the opening in the mounting plate. A cylindrical, open-cell foam collar encircles the fan housing. The collar is sized so that the collar extends a substantial distance upstream past the edge of the collar. The foam collar reduces the acoustic noise from the fan by damping the housing vibration and also by acting as a barrier to muffle sound waves in the air. In addition, the foam collar straightens out the air flow prior to entering the fan blades making it more laminar and less turbulent to increase the efficiency of the fan.

Abstract: Disclosed is a method, and apparatus implementing that method, for synchronizing and managing the "system clocks" maintained by each of a number of processor units forming a multiprocessor system. Based on an averaging technique, the method includes creating a synchronization message by an originator processor unit and routing that message to other of the processor units to obtain clock values representative of each of the system clocks of each processor unit. The average clock value is then determined and that average clock value then rerouted to each of the processor units to permit them to update, if necessary, their individual system clocks to the average of all. The method further includes determining the transit times encountered by the various messages so that each processor unit can adjust the average clock value it will use to update or synchronize its system clock to account for such transit times.

Abstract: An improved EFL gate which provides concurrent true and complementary outputs. An input transistor has its base coupled to an input and its emitter coupled to an emitter of a reference transistor. The reference transistor has its base coupled to a voltage reference and its collector coupled to the base of a true output transistor. The emitter of the true output transistor provides the true output, while its collector is coupled to a voltage supply. A complementary output transistor has its base coupled to the collector of the input transistor with its emitter providing the complementary output. Its collector is coupled to the voltage supply, as is the collector of the input transistor.

Abstract: Apparatus for providing a relatively constant clocking signal to a serial input/output device from a microprocessor regardless of whether the microprocessor is executing a normal instruction cycle or an extended cycle. A state machine is driven by the same clock which drives the microprocessor and a signal from the microprocessor indicating the presence of a normal or extended instruction cycle. The state machine and the clock which drives the microprocessor drive a clocking circuit which produces a first waveform if a normal instruction cycle is being executed, and a second waveform if an extended instruction cycle is being executed. Both waveforms are edge synchronized to the clock which drives the microprocessor.

Abstract: Simplified method and apparatus for performing integrated scrambling and encoding or descrambling and decoding of block code digital transmissions is disclosed. The method involves setting the scrambling length equal to an integer multiple of the block length, and then implementing a pseudorandom number sequence generator within the block length counter. The output of the pseudorandom number sequence generator is then logically combined with the incoming data to provide scrambled data, simplifying the complexity of the encoder or decoder significantly.

Abstract: An improved method for communicating updated information among processors in a distributed data processing system. The system includes a plurality of distributed interconnected processors each having a memory. The method includes the steps of prioritizing the processors into a predetermined order, establishing one of the processors as a control processor for the broadcast of update messages, developing an update message in at least one of the processors, selecting in accordance with the control processor one of the processors which has developed an update message as a sender processor, broadcasting the update message of the sender processor to each of the processors, and causing the next processor in order to be selected as control processor in the event that the former control processor fails in service. As one preferred use, the method enables the system to transmit atomic global update messages with a tolerance to multiple processor faults.

Abstract: Apparatus is disclosed for generating pseudo-random bit patterns that are applied to a data processor, or other digital logic unit, for test purposes. In accordance with the invention, certain of the elemental storage units (e.g., flipflops) of the data processor are designed for two-mode operation: A normal mode of operation during which they operate as a part of the data processor in normal fashion, and a scan mode operation during which the elemental storage units respond to scan control signals to form a number of shift register or scan line configurations for receiving the pseudo-random sequenced or non-random sequenced test patterns generated by the apparatus. During testing, the bit patterns are passed through the scan line configurations and applied to compression circuits where, using cyclic redundancy checking (CRC), compression bit patterns received from the scan lines are achieved.

Abstract: Electronic system grounding includes two system grounding paths for card cage electronic modules, with a first grounding path through the card cage and a second grounding path through the system power supply. The two system grounding paths are used to minimize noise and reduce unwanted induced superimposed transient voltage levels.

Abstract: A digital logic circuit and method for synchronizing the leading edges skewed true-complement signal pair. The circuit is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines.

Abstract: A driver circuit for simultaneously setting up a plurality of output buffers of a 3-stage gate array into and out of a floating state using low control current. A buffer driver transistor is provided for each output buffer with the primary control path of that transistor introducing a control circuit to the respected output buffer. A common driver transistor has a primary current path which provides a control signal to the control electrodes of a plurality of buffer driver transistors. Clamp means are provided for discharging the conductor means to ground upon turn-off of the common driver transistor.

Abstract: A storage unit for an array of modular assemblies, such as disk drives, includes a cabinet having an array of rectangular cavities open toward the front, each for receiving an assembly carrier drawer. Each carrier drawer has electrical connections for receiving an electrical assembly in the drawer. The rear of each drawer has an electrical connection panel for mating a receiving panel connected to the inside back of the cabinet, and associated with the electrical connection panels are pin-and-aperture locating and registering means for precisely aligning the carrier drawer for proper mating electrical contact with the back of the cabinet automatically as the carrier drawer is pushed fully into the cabinet. This enables disk drive maintenance to be performed quickly and efficiently by pulling out a carrier drawer and inspecting, repairing or replacing the modular assembly.

Abstract: A structural support and thin panel assembly wherein the longitudinal axis of the structural support is attached perpendicular to the thin panel comprising a structural member, a thin panel, a female member attached to the structural member and a fastening means removably attaching the female member to the thin panel.

Abstract: An electronic circuit for the generation of multiple breakpoint interrupts uses a plurality of RAMs (random access memory) wherein are stored bits such that, if all of the bit outputs of the RAM are active, then a breakpoint has been recognized. The logical combination of the RAM outputs determines the presence of a breakpoint.

Abstract: A multiprocessor system of the kind in which two or more separate processor modules are interconnected for parallel processing includes interprocessor buses dedicated exclusively to interprocessor communication. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. An enable latch in each port dynamically disables that port from placing any signals on the related input/output bus in response to a failure of any portion of the device controller, and the enable latch is not responsive to the processor module for re-enabling the port.

Abstract: A memory system for a computer detects data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module indicating the status of operations of that memory module and is transmitted to the processor subsystem of the computer for comparison with a signal indicating the status of operations of the processor subsystem to insure that all memory modules and the memory control in the processor are receiving the same commands.

Abstract: In a multiprocessor system of the type in which two or more separate processor modules are connected by an interprocessor bus dedicated exclusively to interprocessor communication for parallel processing, there is provided an input/output system having multiported device controllers connected to the multiprocessor system by input/output buses. Each device controller is shared by pairs of the processor modules, and includes logic that ensures that only one port is selected for access at a time.

Abstract: The disclosure relates to an input-output multiplexer demultiplexer communication channel which transfers data between a communications controller and a multiplicity of radially attached communications ports. Self-clocking serial bit-synchronous data is transferred on two opposing unidirectional data links between the communications controller and the communications channel. Serial bit-synchronous data is transferred between the communications channel and the communications ports. The communications channel uses one-bit-time response round-robin polling when the communications channel initiates transmissions from the communications ports. Data transmissions from the communications controller are multiplexed on-the-fly in the communications channel to one of the communications ports.