Abstract: The invention comprises a method for encrypting data for communication between a host computer and each of a plurality of remote terminals in a network. A method is provided for periodically generating a unique dynamic encryption key for each of said plurality of terminals using a system seed key residing only in the host computer. The dynamic encryption key generated for use by said terminal in encrypting data transmitted to said host computer and for decrypting data received from said host computer. The method includes storing at said terminal the dynamic key previously generated by said host for said terminal.

Abstract: The present invention provides an integrated circuit that has both driver and receiver functions. The circuit of the present invention has two interrelated parts. The first part of the circuit converts true TTL signals to true ECL signals. The second part of the circuit accepts true ECL signals and drives a tri-state true TTL bus. The novel design of the present invention provides a common circuit that acts as an input reference for the circuit that converts true TTL signals to true ECL signals and as a tri-state clamp for the circuit that accepts true ECL signals and drives a tri-state true TTL bus. Using the same circuit components to perform functions in two separate circuits reduces the component count of the resulting circuit and increases the circuit's power/device count figure of merit.

Abstract: An electronic module (6) and integrally mounted latch assembly (2) includes a latch handle assembly (4) mounted to the module and a keeper (8) mounted to a housing (10). The latch handle assembly includes a U-shaped handle (18) having an elongate lever (42) pivotally mounted to one leg (22) of the handle at latch end (46) of the lever. The latch end has a cam surface (64) which engages the keeper. The outer, catch end (44) of the lever is configured to engage a spring-loaded catch button (50) mounted to the other leg (20) of the handle. A disenable switch pin (72) is mounted to the handle to resiliently engage the underside (80) of the lever so that when the lever is in the latched position, the lever keeps the disenable switch pin depressed. The pin is long enough to engage an enable switch (96) within the housing when so depressed.

Abstract: An insertion/extraction mechanism is used to cause blind mateable electrical connectors on an electrical module to engage and disengage mating electrical connectors in a housing by forcing the module to and from its fully inserted position within the housing. The mechanism includes a U-shaped handle pivotally mounted to the module at its ends through elastomeric sleeves. The sleeves are each mounted in a mounting hole in the module and each has a central bore within which a mounting shaft, extending from the handle, is housed. Each end of the handle has a camming surface which engages a pivot pin carried by the housing as the handle is pivoted while inserting the module into and withdrawing the module from the housing. This engagement of the camming surfaces and the pivot pins causes the handle ends and the associated mounting shafts to push radially against the elastomeric sleeves as the handle is pivoted during insertion and extraction.

Abstract: A system for preserving, generating, and merging different versions of a common module that utilizes a line file storing the text of every line in a version and addressing each line with a unique line identifier. Any desired version may be generated directly without creating intermediate versions. The unique line identifiers facilitate a merge operation that does not duplicate lines.

Abstract: A computer program measures the execution of machine code instructions in an executing program. A copy of the measured program is made and selected machine instructions are replaced by interrupt-causing breakpoint instructions. As each breakpoint instruction is executed, the breakpoint is replaced by the actual instruction, and a bit map is updated to indicate execution of the measured instruction. Execution resumes with the actual instruction.

Abstract: A system interconnects electronic modules with one another, to a power supply and to signal lines through a printed circuit board. The modules are electrically connected to traces on the printed circuit board using blind mateable connectors. EMI shielding plates are mounted to the circuit board at the I/O connectors for the external cables. Guide elements, such as pin and socket guides and printed circuit board edge guides, are mounted to the circuit board to guide the blind mateable connectors. The system eleminates the numerous cables which would otherwise be required. The printed circuit board is mounted within the system housing and acts as an air duct barrier to aid proper air circulation. The circuit board also acts as a structured element helping to stabilize the housing and various module supports and serves as a mounting structure for various elements, such as cooling fans.

Abstract: A stack with a unary encoded stack pointer which uses the position of a single bit to point to the top of the stack. A number of multi-bit latches are used to store the data elements in the stack. A serial, bidirectional shift register is loaded with all digital zeros except for a position having a digital one (the pointer) which is coupled to the register containing the top of the stack. As new data elements are pushed onto or popped off of the top of the stack, the pointer is shifted right or left accordingly.

Abstract: A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processor are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.

Abstract: A removable power supply interlock and extraction mechanism (2) includes a switch guard (16), mounted to the front panel (14) of a module (4), movable between a safe position when the power switch (12) is off to keep it off, and a working position, at which the switch can be freely turned on and off. When the module is being inserted into an electrical unit (16), an actuator (34), mounted to the front panel, is rotated in its insertion rotary direction (50) so the switch guard moves from its safe to its working position; simultaneously a latching element (62) on the actuator engages a latching surface (60) on the unit so to drive the module into the unit until the connectors on the module and unit are fully connected. To remove the module, the power switch is first turned off.

Abstract: Apparatus is disclosed for forming scan data path subchains from the elemental memory units of a digital system, and interconnecting the scan data path subchains to form an extended serial shift register for scan testing. The method and apparatus for forming the interconnections ensures that data is passed from one subchain to another without data being lost due to clocking irregularities.

Abstract: A method, and apparatus implementing that method, for monitoring a synchronization circuit to ensure proper operation thereof. The synchronization circuit is of the type that receives asynchronously occurring input pulses to produce therefrom representations of the received input pulses, having state transitions synchronized to the state transitions of a periodic clock signal. The invention also receives the input pulses and the synchronized representation of those pulses, to ensure that for every input pulse there is provided a synchronized pulse by the synchronization circuit.

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and return to a desired line after a delayed call.

Abstract: A parity regeneration and self-check technique is used for detecting and locating errors in data communicated to, through, and from a digital subsystem. The invention utilizes a parity check associated with a data input of the subsystem, regenerating parity for data communicated from an output of the subsystem, checking the regenerated parity and comparing that check with other checks.

Abstract: A temperature alarm includes a thermostat for actuating an audible alarm, a control panel-mounted LED and a circuit board-mounted LED. The audible alarm, once actuated by the thermostat, can be temporarily disabled by the user by actuating a disable timer connected to the audible alarm. After a period of time the timer times out to return control of the audible alarm to the thermostat. The panel LED is illuminated continuously while the chosen temperature value is exceeded. The circuit board LED is mounted to a circuit board within the equipment housing. Once illuminated by the thermostat, the circuit board LED remains actuated regardless of the temperature to provide an indication to a service technician that the chosen temperature was exceeded since the last servicing. The circuit board-LED, coupled to a latching relay also mounted to the circuit board, is extinguished by manually resetting the latching relay.

Abstract: A converter for coupling a single-ended and a differential SCSI bus that facilitates the use of the ARB, SELECTION, and RESELECTION phases of the SCSI protocol.

Abstract: The present invention provdes a circuit for driving a TTL bus from an ECL circuit. The circuit of the present invention speeds up the "tri-state" to "active" transition by eliminating the need to pass the tri-state signal through a translator and buffer. A tri-state control circuit accepts true ECL input directly, thus eliminating the delay, power and density "cost" of the translator and buffer circuits. This circuit further improves the delay performance of tri-state/active transitions by restricting device saturation to low levels.

Abstract: Checking method and apparatus for monitoring the proper operation of a state machine of the type operable to produce control signals that in turn, cause other digital apparatus to produce responsive signals. Part of the checker apparatus, in effect, emulates the digital apparatus, receiving the control signals to produce therefrom emulated response signals that, when compared to the control signals, provide an indication of correct operation of the state machine means and associated circuitry.

Abstract: A cross-coupled checking circuit is disclosed in which two identical integrated circuit chips are configured in a complementary manner and connected in parallel to the same inputs and outputs. One chip drives the data output data and the other chip drives the check symbol output corresponding to the output data. Each chip generates internal results and compares them to the output driven by the other chip.

Abstract: A special-purpose, microprogrammed digital subsystem sequences through stored lists of microinstructions to produce various control signals. In response to address signals provided by an address generator, the microinstructions are accessed in pairs: A primary microinstruction and a branch or target microinstruction. For the most part, only the primary microinstruction is decoded and executed. However, certain of the ones of primary microinstructions are of the type that require a decision to be made, and the microinstruction stream branches to one of two choices depending upon the outcome of the decision. The target microinstruction forms the first microinstruction of one of the available microinstruction branches, and, if this branch is taken, is executed in parallel with the branch to avoid time penalties. An additional aspect of the invention is that the address generator, which provides address signals to a memory that stores the microinstructions, is capable of functioning as a timer circuit.