Abstract: An improved network timer for use in a network node, preferably a reliable mode network employing IPX/SPX data packets on workstations or computer. A method and apparatus is disclosed for use by a workstation node whereby a plurality of data packet timers may be supported and set, triggered and deleted in a maximum of K operations or time increments, where K is a constant and not a function of N.

Abstract: A computer architecture has a plurality of processing cells interconnected to perform programming tasks. Each cell contains both memory and processing elements. Memory packets contain an instruction, a data element, and a pointer to another memory packet. Tasks are executed by following a linked list of memory packets. Transmission packets communicate instructions and register values along the linked list. A plurality of computer processes may be executed simultaneously.

Abstract: Two identical streams of multi-bit symbols are received by a pair of storage elements, each having multiple locations and first and second pointer counters respectively identifying the locations at which received symbols are stored and from which stored symbols are retrieved. The storage elements are synchronized by providing each with a SYNC symbol that, when detected, causes the pointer counters to be placed in a predetermined (reset) state on one transition of a SYNC clock signal, releasing the pointer counters at the same time on a following transition of the SYNC clock signal.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: Link Ids are associated with file handles in a directory structure in a computer operating system. The Link Ids allow a file handle to be mapped uniquely to a pathname for a file associated with the file handle. In one implementation lists are used to facilitate fast searching of directory structures for a name associated with a Link Id. The list includes entry pairs where each entry pair is a Link Id and a directory number where a name associated with the Link Id may be found.

Abstract: A power switching circuit module includes two power rails coupling independent power supplies to the input of a DC controller and test circuits to detect latent faults in power mixing devices included in the circuit.

Abstract: An application specific integrated circuit (ASIC) includes ASIC logic, test logic, dual function input test cells and dual function output test cells. The test logic with the input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins while reducing both the gate count and signal time delay associated with the input and output test cells. Each input test cell includes a boundary scan circuit means and a built-in self-test circuit means. An input test cell has a signal propagation time delay for a signal, that travels from an input pin to an ASIC logic input line, equivalent to one two-to-one multiplexer signal propagation delay. Hence, while the input test cell has the capability of both built-in self-test and boundary scan testing, the dual capability is achieved without incurring a signal propagation time delay for each capability.

Abstract: A processor system comprising a number of data handling units interconnected by a system bus operates according to a novel protocol wherein one of the number of data handling units issues a buss request signal together with a separate arbitration signal uniquely identifying the data handling unit requesting access to the system bus. Distributed priority determination logic, located in each data handling unit, allows each data handling unit requesting bus access at the same moment in time to independently and unilaterally ascertain who has access. The bus request signal remains asserted to hold off any additional requests for bus access until all data handling units first requesting access have been serviced.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.

Abstract: A modular bus routing system incorporates segments of a plurality of parallel buses in a substrate on which device connectors are strategically located. Each end of each bus segment is coupled to a connector mounted on the substrate and interconnection between bus segments on different substrates is afforded by a flexible cable containing bus conductors of controlled length and electrical characteristics. A plurality of personality cards provide several different types of bus segment interconnection so that different segments can be terminated, or jumpered to other segments on the substrate. By selecting different personality cards, the plurality of bus segments on a given substrate can be configured as a single serially connected bus, two, four or eight buses. The system affords wide flexibility for computer systems using host initiators and mass storage devices to provide a highly configurable computer system using such elements.

Abstract: An apparatus and method of correcting parity errors in a fault tolerant computer system. Data and associated parity are checked in parallel with use of the data by an ALU. Upon detection of an error, a controller causes the ALU to pass the input data unchanged and associates a correct parity with the input data. The correct parity generation is done in parallel with ALU processing to permit rapid reassociation of data and its correct parity. The reassociated data is returned to the ALU for processing.

Abstract: A boundary scan bus error reporting circuitry loads an unused sentinel bit pattern into the boundary scan instruction register in a conventional error reporting boundary scan test system. The unused sentinel bit pattern signifies that a fault exists somewhere upstream of the instruction register in the boundary scan circuitry associated with a specific integrated circuit. The special sentinel pattern is loaded into the instruction register in response to an illegal instruction control signal generated by an instruction decoder coupled to the instruction latch in the boundary scan architecture.

Abstract: A structured query language (SQL) grouping and aggregation system and method that incorporates hash-based techniques, several overflow handling strategies and statistics-based process-selection criteria. The method can execute SQL group-by queries on distributed database tables or tables stored locally to the database management system (DBMS) processor executing the grouping method. Hash-based techniques allow groupings and aggregates to be generated on the fly through the use of partial aggregates maintained in primary memory. Where primary memory is limited, groups and aggregates are still generated for as many groups as can be maintained in primary memory, while various overflow procedures are provided for buffering ungrouped data and writing that data to an overflow disk file for later processing. In one overflow procedure, raw data from groups that cannot be aggregated in primary memory are buffered then written to the overflow disk file.

Abstract: Disclosed is apparatus for aligning and mounting electrical components, such as packaged integrated circuits, to a printed circuit board. During an alignment phase, a sample component is attached to a stand-in circuit board at a component site. A base plate, having alignment elements, is then fitted to the board proximate the attached sample component. Next, a chuck is mounted to the sample component, and an alignment plate positioned to engage the alignment elements of the base plate, and affixed to the chuck, forming a chuck assembly that is aligned to the base plate and registered to the component site of the circuit board. During the production phase the base plate is placed on a printed circuit board at a location substantially identical to that on the stand-in printed circuit board.

Abstract: A multi-processor system having mirrored memory units accessible by either processor. The term "mirrored memory" in the context of the present invention describes the ability of each of the processors to directly READ and WRITE the contents of its own local random access memory (RAM) unit and in the local RAM unit of the other, remote processor. The mirrored memory of the present invention comprises two units of triple-ported RAM, each unit interconnected by a pair of interprocessor busses to the corresponding triple-ported RAM of the remote processor. "Triple-porting" describes the three input/output ports available for accessing a RAM unit. An internal port is used by a processor to access its local RAM, while the other two ports are provided so that the same RAM can be accessed by the remote processor through the paired interprocessor busses. Each processor may READ or WRITE its own local RAM, the remote processor's RAM, or both RAM's during a single operation.

Abstract: A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.

Abstract: A power mixing apparatus for mixing current from a first and a second power rail includes a first enabling circuit to provide a first enabling signal, a second enabling circuit to provide a second enabling signal, a first inrush limiter to output a first current in response to the first enabling signal, a second inrush limiter to output a second current in response to the second enabling signal, a first open-circuiting circuit to decouple the first enabling circuit from the first inrush limiter when the first open-circuiting circuit is open-circuited, a second open-circuiting circuit to decouple the second enabling circuit from the second inrush limiter when the second open-circuiting circuit is open-circuited, a first isolation circuit to isolate the first inrush limiter from the second current, a second isolation circuit to isolate the second inrush limiter from the first current, and a direct-current converter to convert the first and the second current in response to the first enabling signal and in respo

Abstract: A fault tolerant computer system having a plurality of processor modules having independent clocks for processing an instruction stream, global memory accessible by all of the processor modules, and a local memory configured within each processor module and clocked synchronously therewith. The local memory is periodically refreshed between accesses to the local memory by the processor. Warning signals indicating a potential access to the local memory are provided to a refresh controller and the local memory is refreshed or the refresh is aborted depending upon the number of clock cycles available before a local memory access occurs. A speculative refresh may be stalled until a processor instruction is decoded to determine whether a local memory access is requested or not.

Abstract: A master clock signal, used to operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or that communicate such signals to a destination external to the integrated circuit.