Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A detachable dolly for moving heavy electronic equipment employs a mounting bracket and a wheel assembly, the mounting bracket having a support plate and a mating flange. The mounting bracket is secured to the equipment by the support plate, having at least one lifting dowel, and at least one mounting bolt. The wheel assembly has a wheel mounted within a wheel bracket and a rotation adjustment mechanism for raising and lowering the wheel and is detachably engaged with the mating flange on the mounting bracket by the use of a mating member. The mating member is movably coupled with the adjustment assembly such that when the mating member is engaged with the mating flange, rotation of the adjustment assembly serves to vertically raise or lower the equipment.

Abstract: A data communication system embodying an apparatus and a method provides simultaneous paths between a plurality of transmit ports and a plurality of receive ports for transmitting therebetween data identifying their destination receive ports. Such data are signals which are constructed in accordance with a standard serial protocol for frame element communication, such as HDLC (High-level Data Link Control). The system is assembled in a chassis containing a backplane and multiple cards having transmit and receive ports through which the cards couple the backplane.

Abstract: A clock synchronization system includes a clock generator for producing first and second system clock signals that are each received by corresponding ones of a pair of integrated circuits from which the integrated circuits each produce secondary clock signals. The clock system includes synchronizing circuitry that receives the secondary clock signals to determine the phase difference between them, and delaying one of the system clock signals, relative to the other, in a manner that results in the state transitions of the secondary clock signals occur within a period of time of each other.

Abstract: A scannable logic unit includes one or more storage registers that maintain copies of data communicated from the scannable unit to registers in a nonscannable unit. When the scannable unit is subjected to a scan test, the registers will contain state information respecting that transfer to the nonscannable unit. When the scannable and nonscannable units are placed in a run condition, the registers supply to the nonscannable unit state information for continuing operation.

Abstract: A computing system, having an input/output bus for communicating data thereon, is connected to a network by a pair of network controller devices. Each of the network controller devices, in turn, connect to a corresponding one of a pair of multi-ported network repeater elements which are, in turn, connected to one another by a pair of network links. At least one workstation is connected to each of the network repeaters. One of the network controllers is initially selected as a primary data communicating path from the computing system to the network. The network controllers periodically transmit messages to one another, and if receipt of those messages by the primary network controller is noted, the selection of the primary controller will be switched to the other.

Abstract: A fault-tolerant control and monitoring system for fan assemblies used in electronic equipment. The fan control and monitoring system of the present invention reduces the probability of high temperature damage due to power failure by using a power mixing circuit that provides redundant power to the fans. The system includes means for detecting faults in the power mixing circuit. The system of the present invention further includes means for measuring the exact speed of the fans, as well as means for finer control of fan speed. Physical presence of fan unit is detected without additional pin requirements.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A regulator circuit supplies a regulated low, DC voltage that is derived from an unregulated voltage provided by a pair of redundant batteries. The regulator circuit comprises regulation control that responds to a feedback signal developed from monitoring the regulated voltage to maintain the regulated voltage at a desired level. Battery monitors supervise the voltage levels of the batteries used, and shut down the regulator when the battery voltages drop below a predetermined voltage level to preserve battery life.

Abstract: A diagnostic system for diagnosing states of circuit elements is described, wherein scannable circuits can be scanned without disturbing the state of unscannable circuits or violating protocols of busses on which unscannable devices are attached. One unscannable device is a standardized microprocessor. A processor interface circuit is coupled between the microprocessor and scannable processor circuits, via a processor bus, to insulate the scannable processor circuits from the unscannable microprocessor. The processor interface circuit is also scannable, including memory elements which affect the bus, by preventing a scan when the bus is in use. A scan is prevented through the use of a maintenance request signal from a scan controller to the processor interface circuit, and one or more maintenance approval signals from the processor interface circuit to the scan controller.

Abstract: An application specific integrated circuit (ASIC) includes ASIC logic and test logic that includes a fail-safe circuit and test logic circuitry. The test logic in conjunction with input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins. The test logic generates several control signals that can affect operation of the ASIC logic. If any one of these signals is driven active by either a failure or a defect, the ASIC logic would be rendered inoperative. Consequently, each of these control signals is routed to the fail-safe circuit. These control signals include, for example, tri-state and reset signals and other control signals generated by test logic circuitry for the built-in testing of the ASIC.

Abstract: A computer architecture has a plurality of processing cells interconnected to perform programming tasks. Each cell contains both memory and processing elements. Memory packets contain an instruction, a data element, and a pointer to another memory packet. Tasks are executed by following a linked list of memory packets. Transmission packets communicate instructions and register values along the linked list. A plurality of computer processes may be executed simultaneously.

Abstract: A programmable system for checking for protocol errors in a communication system includes a matrix for generating error checking signals selected by data fields utilized to implement a communication. If the configuration or protocol is changed the system facilitates reprogramming to compensate for the change.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: A computer system employs multiple CPUs, all executing the same instruction stream, with multiple, identical memory modules storing duplicates of the same data and accessable by all the CPUs, providing global memory. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously. Each CPU has its own fast cache and also a local memory not accessable by the other CPUs. A hierarchical virtual memory management arrangement for this system employs demand paging to keep the most-used data in the local memory, page-swapping with the global memory. Page swapping with disk memory is through the global memory; the global memory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory. The operating system kernal is kept in local memory. This arrangement is particularly useful in fault-tolerant computer systems.

Abstract: A drawer, of the type constructed to carry electronic apparatus, and to be inserted into a cabinet, includes at least two separate connector parts adapted to mate with corresponding connector parts mounted on a backwall or backplane of the cabinet. An alignment mechanism, comprising a pair of alignment pins extending from the cabinet backplane, and multiple pairs of apertures associated with the drawer, each pair corresponding to one connector, function to align the separate connector parts on the drawer to those mounted on the backplane of the cabinet.

Abstract: A method and apparatus for synchronizing a plurality of processors. Each processor runs off its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor.

Abstract: A system and method for ensuring the completion and integrity of data modification operations to a redundant array data storage system and for ensuring the integrity of redundancy values in such a system.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A high speed, synchronous, processor bus is physically and electrically extended by a bus extension unit to provide data communication between a number of data handling units. The bus extension unit intercouples a system bus to an extended buses for communicating information therebetween. The extension monitors both bus and, upon recognition of an initiation for an information transfer transaction from one bus to the other, will relay the initiation of the transaction, implement the transaction, then relay back any handshake signals that form a part of the transaction, all with a minimum delay of one bus cycle.