Patents Assigned to Technologies AG
  • PREDISTORTION OF AMPLIFIER INPUT SIGNALS
    Publication number: 20110025414
    Abstract: Described herein are devices, methods, and techniques related to predistortion of amplifier signals based on an operating condition. Predistortion techniques are described that mitigate or eliminate the effects of variable operating conditions, including nonlinear effects, on amplified signals. Nonlinearities may be mitigated by compensating at a baseband signal prior to amplification, generally using scaling and a static characteristic that is valid for a broad range of operating conditions.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 3, 2011
    Applicant: Infineon Technologies AG
    Inventors: Norman Wolf, Jan-Erik Mueller
  • Decompression sprue bush and decompression machine nozzle
    Publication number: 20110027411
    Abstract: The present invention concerns a transfer element (1, 9) for an injection molding system comprising a flow lumen for a plasticised plastic material. To provide a transfer element for an injection molding system, which makes it possible to further increase the material throughput of the injection molding system without having to tolerate increased wear of seals and other system components, it is proposed in accordance with the invention that it has a device for degassing of the flow lumen.
    Type: Application
    Filed: September 21, 2007
    Publication date: February 3, 2011
    Applicant: MHT Mold & Hotrunner Technology AG
    Inventors: Wolfgang Puest, Matthias Brinzing
  • METHOD FOR INCREASING THE AVAILABILITY OF DISPLACEMENT/POSITION MEASURING SYSTEMS ON THE BASIS OF POTENTIOMETERS WITH A SLIDER TAP
    Publication number: 20110025353
    Abstract: The disclosure relates to a method for increasing the availability of displacement/position measuring systems on the basis of potentiometers with a slider tap in a closed control loop, the controller of which is formed by a microcontroller which is supplied with the position of the slider via an analog/digital converter. The position of a defective slider position of the potentiometer is determined within the active process task by evaluating an available control loop variable, and the reference variable of the control loop is overloaded in a defined manner such that the defective slider position is passed over during the displacement/position measurement and an intact slider position is reached.
    Type: Application
    Filed: July 23, 2010
    Publication date: February 3, 2011
    Applicant: ABB Technology AG
    Inventors: Stefan Tabelander, Thomas Kleegrewe, Andreas Wahlmann
  • STACKED SEMICONDUCTOR CHIPS
    Publication number: 20110024918
    Abstract: Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements.
    Type: Application
    Filed: October 14, 2010
    Publication date: February 3, 2011
    Applicant: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Recai Sezi, Thorsten Meyer, Gottfried Beer
  • DETERMINING A BUS BAR VOLTAGE
    Publication number: 20110029149
    Abstract: A Substation Automation (SA) system in high or medium voltage power networks is provided for determining a bus bar voltage at a first node. The disclosure replaces a ‘real’ voltage transformer with an intelligent electronic device (IED) and/or a ‘virtual’ voltage transformer (VT), which determines the bus bar voltage at the first node from a first bay connected to the first node. The IED receives network message from a second IED of the SA system, indicating the bay voltage of the first bay connected to the first node. The IED also receives switch status of the switching device arranged between the first bay and the first node, from a third IED. Depending upon the switch status, the IED establishes the bay voltage as the bus bar voltage at the first node.
    Type: Application
    Filed: August 3, 2010
    Publication date: February 3, 2011
    Applicant: ABB Technology AG
    Inventor: Wolfgang WIMMER
  • HIGH VOLTAGE DRY-TYPE REACTOR FOR A VOLTAGE SOURCE CONVERTER
    Publication number: 20110025447
    Abstract: A high voltage dry-type reactor is series-connected via a first terminal to an AC supply voltage and via a second terminal to the AC phase terminal of a high voltage converter and includes a cylindrical coil of insulated wire. In order to protect the reactor from a damaging DC field, the reactor further includes a metallic or resistive electrostatic shield which is connected to a same DC potential as the converter.
    Type: Application
    Filed: August 29, 2007
    Publication date: February 3, 2011
    Applicant: ABB Technology AG
    Inventors: Björn Jacobson, Gunnar Asplund
  • MODULAR TEST PLUG
    Publication number: 20110028031
    Abstract: A modular test plug assembly is disclosed having a design which may be arranged in a plurality of different configurations. The test plug assembly includes a plurality of modules, having blades for insertion into a test switch assembly. The modules are positioned in a stacked arrangement and are secured together by end plates and a rod extending therebetween.
    Type: Application
    Filed: July 22, 2010
    Publication date: February 3, 2011
    Applicant: ABB Technology AG
    Inventors: Andrew Bower, Tim Masters, Roy Ball
  • Combined mixer and polyphase decimator
    Patent number: 7881405
    Abstract: Some embodiments discussed relate to an apparatus and method for processing signals, comprising receiving an input signal and forming a stream of digital samples of the input signal by sampling at a sampling frequency and mixing the stream of digital samples using a mixer sequence having a sine sequence and a cosine sequence based on the sampling frequency to generate an input sequence, each of the sine sequence and the cosine sequence including a plurality of components in an arrangement such that at least one of the components has a zero value and the remaining components has a non-zero value, and filtering the input sequence using a plurality of polyphase filter parts, each corresponding to the non-zero components of the sine sequence and the cosine sequence, and selectively combining the outputs of the polyphase filter parts to generate an in-phase sequence and a quadrature sequence.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Andreas Menkhoff
  • Modulated-Vt transistor
    Patent number: 7880202
    Abstract: A semiconductor field effect transistor can be used with RF signals in an amplifier circuit. The transistor includes a source region and a drain region with a channel region interposed in between the source and drain regions. The transistor is structured such that the threshold voltage for current flow through the channel region varies at different points along the width direction, e.g., to give an improvement in the distortion characteristics of the transistor.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Peter Baumgartner
  • Semiconductor module
    Patent number: 7879652
    Abstract: A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 ?m.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Klaus Schiess
  • Substation automation system with increased availability
    Patent number: 7882220
    Abstract: In automation systems, such as Substation Automation systems, the mean time to repair is reduced by remote reconfiguration and start-up of a replacement or spare Intelligent Electronic Device (IED), leaving some more hours for the maintenance personnel to repair an inactive or faulty IED. The time for the actual repair is irrelevant for the system availability as long as it is short enough compared to the IED failure rate. Exemplary embodiments can provide nearly the same availability as a hot-standby configuration, but without the need for doubling all the essential IEDs. Additionally, spare IEDs are supervised to be healthy, and a fault of the spare IED being detected before it is put in use. Only one spare online IED is needed for each set of IEDs of the same type connected to the same station bus and process bus.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 1, 2011
    Assignee: ABB Technology AG
    Inventor: Wolfgang Wimmer
  • Capacitive sensor and measurement system
    Patent number: 7880481
    Abstract: A system includes a capacitive sensor including a first electrode and a second electrode. The system includes a measurement system configured to sense a capacitance between the first electrode and the second electrode and apply a first offset to the sensed capacitance to provide an offset compensated capacitance.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hubert Zangl, Thomas Bretterklieber, Gert Holler, Georg Brasseur, Tobias Werth, Dirk Hammerschmidt, Mario Motz
  • Integrated circuit arrangement comprising isolating trenches and a field effect transistor
    Patent number: 7880264
    Abstract: A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Ronald Kakoschke, Franz Schuler
  • Lithography system with illumination monitor
    Patent number: 7880863
    Abstract: A lithographic system including a light source configured to provide a light beam, a mask stage configured to hold a mask having a mask pattern, a wafer stage having a surface configured to hold a wafer having a plurality of dies, and an illumination monitor having a receiver disposed at the surface of the wafer stage and a polarimeter. A projection system is configured to shape and direct the light beam via the mask pattern to form an exposure beam and to individually expose each die with the exposure beam, and is configured to shape and direct the light beam to form a monitor beam and to expose the receiver with the monitor beam. The receiver is configured to communicate the monitor beam to the polarimeter which, based on the monitor beam, is configured to provide an illumination signal representative of properties of the light beam as it passes through the lithographic system.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Vlad Temchenko
  • Semiconductor device comprising a semiconductor chip stack and method for producing the same
    Patent number: 7880285
    Abstract: A semiconductor device includes a semiconductor chip stack having at least one lower semiconductor chip as a base of the semiconductor chip stack, and at least one upper semiconductor chip. An insulating intermediate plate is arranged between the semiconductor chips. Connecting elements wire the semiconductor chips, the intermediate plate and external terminals to one another.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Khalil Hosseini, Joachim Mahler
  • Method of making a transformer having a stacked core with a split leg
    Patent number: 7877861
    Abstract: The present invention is directed to a method of making a transformer having a stacked core, which includes top and bottom yokes and first and second outer legs. The core also includes an inner leg that is formed from a pair of stacked plates, which abut each along a seam that extends in the longitudinal direction of the inner leg. Each of the upper and lower yokes may be formed from a single stack of plates, or a plurality of stacks of plates. Each of the inner and outer legs may also be formed from a single stack of plates, or a plurality of stacks of plates. The cross-section of the core may be rectangular or cruciform.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: February 1, 2011
    Assignee: ABB Technology AG
    Inventors: William E. Pauley, Jr., Charlie H. Sarver, Rush B. Horton, Jr.
  • Semiconductor chip comprising a metal coating structure and associated production method
    Patent number: 7880300
    Abstract: A semiconductor chip (1) has a metal coating structure (2) which has on an active upper side (3) of the semiconductor chip (1) at least one lower metal layer (8) with copper or copper alloy, on which a central metal layer (9) with nickel is arranged. The metal coating structure (2) is terminated by an upper metal layer (10) of palladium and/or a precious metal. The central metal layer (9) with nickel and/or nickel phosphide has a rough interface (11) with respect to the plastic package molding compound surrounding the metal coating structure (2).
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober
  • Wafer and a method for manufacturing a wafer
    Patent number: 7879699
    Abstract: A wafer includes a wafer frontside and a region adjacent to the device surface, wherein the region includes vacancy-oxygen complexes and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Hans-Joerg Timme, Helmut Strack
  • Method for connecting a die assembly to a substrate in an integrated circuit and a semiconductor device comprising a die assembly
    Patent number: 7880277
    Abstract: A semiconductor device includes a substrate, a die assembly attachable to the substrate and a flexible strip extending over the substrate and the die assembly. The flexible strip has one or more routing circuits carried thereon. The die assembly and the substrate are arranged to be electrically connected through the one or more routing circuits carried on the flexible strip.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Alvin Seah, Elstan Anthony Fernandez
  • Integrated circuit arrangement
    Patent number: 7880477
    Abstract: An integrated circuit arrangement has a signal input 20 and a signal output 60, a signal processing unit 100 which is connected to the signal input 20 and to the signal output 60, a noise source 50 for generating a noise signal, and a noise line 55 which connects the noise source 50 to the signal input 20.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Johann Peter Forstner