Abstract: A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width.

Abstract: A transmitter arrangement includes a first and a second phase-locked loop, each having a power amplifier. The first phase-locked loop generates a first amplified oscillator signal depending on a first input signal representing a first phase information, wherein a first feedback signal for the first phase-locked loop is derived from the first amplified oscillator signal. Accordingly, the second phase-locked loop generates a second amplified oscillator signal depending on a second input signal representing a second phase information. A second feedback signal for the second phase-locked loop is derived from the second amplified oscillator signal. The transmitter arrangement further includes a summation element to combine the amplified first oscillator signal and the amplified second oscillator signal to an output signal.

Abstract: Circuit for calculating a logic combination of two encrypted input operands recieves first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge cycle, and outputs a dual-rail result signal comprising encrypted result values in the calculation cycle and precharge values in the precharge cycle. The data and encrypted result values are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule. A logic circuit determines the encrypted result values according to the logic combination from the data and encryption values, and outputs the encrypted result values in the calculation cycle.

Abstract: A transformer having high and low voltage coils mounted to legs of a core is provided. Each low voltage coil includes conductor sheeting having opposing first and second ends and opposing first and second side edges. A pair of coil bus bars is provided for each low voltage coil. Each coil bus bar has first and second portions, wherein the first portion has a width that is more than one and a half times greater than a width of the second portion. Each coil bus bar is secured to the conductor sheeting of its low voltage coil such that the first portion of the coil bus bar is disposed at the first side edge of the conductor sheeting and the second portion of the coil bus bar is disposed at the second side edge of the conductor sheeting.

Abstract: A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal.

Abstract: Implementations are presented herein that include a level shifter circuit.

Abstract: Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

Abstract: Aspects of the present invention include a semiconductor device and method. In a transition region of a semiconductor material region, a near-surface compensation doping area with a conductivity type, which is different than the conductivity type of a transition doping area of the semiconductor material region, is provided in the surface region of the semiconductor material region. The doping of the near-surface compensation doping area of the semiconductor device at least partially compensates for the doping in the transition doping area.

Abstract: An electronic component has at least two semiconductor devices, a contact clip and a leadframe with a device carrier portion and a plurality of leads. The contact clip extends between the first side of at least two semiconductor devices and at least one lead of the leadframe to electrically connect a load electrode of the at least two semiconductor devices to at least one lead.

Abstract: A semiconductor module has at least two semiconductor chips (4, 5) with at least one first and one second electrode (12, 13) on their first sides. Each semiconductor chip (4, 5) has a third electrode (14) on its second side (16). A chip arrangement within the semiconductor module (1) is provided such that the electrodes (12, 13) on the first sides of the semiconductor chips (4, 5) are oriented toward a second side of the semiconductor module (1) and the third electrodes (14) on the second sides (16) of the semiconductor chips (4, 5) are oriented toward a first side of the semiconductor module (1). For this purpose, external terminals (19, 20) on the second side of the semiconductor module (1) are directly coupled to the electrodes (12, 13) of the first sides and connecting elements (22) electrically couple the third electrodes (14) to corresponding external terminals (21).

Abstract: A DC-to-DC converter includes a switching control circuit adapted to provide a control signal having a duty cycle. A switching regulator is adapted to receive both a supply voltage having the first voltage level and the control signal. The switching regulator is further adapted to provide an output signal at the second voltage level as a function of both the supply voltage and the control signal. In addition, a current sensing circuit is adapted to provide at least one alarm signal based the duty cycle of the time-varying signal. Other systems and methods are also disclosed.

Abstract: A water-based coagulating and hardening accelerator for hydraulic binding agents, comprising sulfate, aluminum and organic acid. The molar ratio of aluminum to organic acid is less than 0.65. Preferably, the molar ratio of aluminum to carboxylic acid is less than 0.60 and greater than 0.38.

Abstract: An integrated circuit and method of making it, includes a semiconductor substrate and a support layer disposed on the semiconductor substrate. A gate insulator including a support layer doped using a noise-reducing dopant can be disposed on the semiconductor substrate. A gate stack can be disposed on the gate insulator.

Abstract: Leadframe for a semiconductor package and manufacturing from such leadframe including a plurality of connection leads supported in a frame. Die mounting plate is centrally located in the leadframe and is supported by a plurality of support leads which are electrically connected to the die mounting pad and extending in a direction outwardly therefrom towards the frame. Each support lead is formed with a connection pad portion and a down set link portion. Each connection pad portion is spaced from the die mounting plate and is connected to a conductive bonding ground wire from a semiconductor device mounted on the die mounting plate. Each down set link portion is electrically connected to the die mounting pad and supports the die mounting pad in a spaced arrangement from the connection leads. The connection pad portion and the down set link portion overlap, in the direction of extension of the support lead.

Abstract: A differential clock pulse compensation is performed between the clock-pulse system (23) of a digital line-connected data interface and the asynchronous clock-pulse system (22) of a digital wireless data interface. A characteristic variable (20, 21) for the asynchronous differential clock pulse between the clock-pulse systems (22, 23) is monitored hereby. The data rate of the data (15, 16) transmitted over the line-connected data interface is adapted depending on the characteristic variable (20, 21).

Abstract: A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Abstract: A semiconductor device (10) includes a semiconductor body (12) of a first conductivity type (e.g., p-type). A first doped region (14) of a second conductivity type (e.g., n-type) is disposed at an upper surface of the semiconductor body (12). A second doped region (16) of the second conductivity type is disposed at the upper surface of the semiconductor body (12) and is separated from the first doped region (14) by an isolation region (18). A first contact (26) overlies and is electrically coupled to the first doped region (14) and a second contact (28) overlies and is electrically coupled to the second doped region (16). A third doped region (32) of the first conductivity type is disposed within the semiconductor body (12) beneath the first doped region (14).

Abstract: A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.

Abstract: A method for the planar joining of components of semiconductor devices involves coating the components with diffusion materials on their upper sides and rear sides, respectively. Subsequently, the components to be joined one on the other are introduced into a reducing atmosphere. The components are aligned and a compressive pressure is exerted on the aligned components. While heating up the components to be joined in the reducing atmosphere to a diffusion joining temperature, isothermal solidification takes place, the diffusion joining temperature lying below the melting temperature of the forming diffusion joint of the joined material.

Abstract: A carrier arrangement having a carrier configured to fix a semiconductor chip, contacts located on the carrier and configured to make contact with the semiconductor chip, and an overvoltage protection in a form of a spark gap arrangement formed between the contacts.