Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 11562790
    Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array based on the read request. The control circuit is additionally configured to count a number of the plurality of memory cells that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit is further configured to apply a second voltage at the second duration to the memory array. The control circuit is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Riccardo Muzzetto, Ferdinando Bedeschi
  • Patent number: 11560266
    Abstract: A food delivery enclosure for delivering groceries includes a low insulation zone and a high insulation zone. The low insulation zone includes energy packs, such as chill packs or hot packs and food items suitable for contact with the energy packs. The high insulation zone is above the low insulation zone and includes food items that are not suitable for contact with the energy packs.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 24, 2023
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Karthik Kumar
  • Patent number: 11563024
    Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Aaron R. Wilson, Paolo Tessariol
  • Patent number: 11563682
    Abstract: In one embodiment, a method generally includes a first edge (E) node in a network receiving an encapsulated data packet, wherein the encapsulated data packet comprises an outer header and a data packet, wherein the outer header comprises a first router locator (RLOC) corresponding to the first E node, wherein the data packet comprises an internet protocol (IP) header, and wherein the IP header comprises a destination endpoint identification (EID) corresponding to a host H. The first E node determines whether the host H is attached to the first E node. And in response to the first E node determining the host is attached to the first E node, the first E node forwards the data packet to the host H. The first E node receives a message from another node after the host H detaches from the first E node and reattaches to another E node, wherein the message comprises the destination EID.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 24, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sanjay K. Hooda, Victor M. Moreno, Satish Kumar Kondalam
  • Patent number: 11563936
    Abstract: A video signal processing method comprises the steps of: receiving information for prediction of a current block; determining whether or not a merge mode is applied to the current block on the basis of the information for prediction; when a merge mode is applied to the current block, obtaining a first syntax element indicating whether or not a combined prediction is applied to the current block, wherein the combined prediction indicates a prediction mode that combines inter-prediction and intra-prediction; generating an inter-prediction block and an intra-prediction block of the current block when the first syntax element indicates that the combined prediction is applied to the current block; and generating a combined prediction block of the current block by weighted-summing the inter-prediction block and the intra-prediction block.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: January 24, 2023
    Assignee: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.
    Inventors: Geonjung Ko, Dongcheol Kim, Juhyung Son, Jaehong Jung, Jinsam Kwak
  • Publication number: 20230019926
    Abstract: A semiconductor structure includes a substrate, a gate structure, a cover layer and a first sacrificial structure. The substrate includes discrete semiconductor channels arranged at a top of the substrate. The gate structure is disposed in a middle region of a semiconductor channel, and includes a ring structure and a bridge structure. The ring structure encircles the semiconductor channel, and the bridge structure penetrates through the semiconductor channel and extends to an inner wall of the ring structure along a penetrating direction. The cover layer is located between adjacent semiconductor channels, and includes a first communication hole. The first sacrificial structure is located on the cover layer, and includes a second communication hole. An inner sidewall of the second communication hole has an irregular shape.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 19, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: SEMYEONG JANG, JOONSUK MOON, Deyuan XIAO
  • Publication number: 20230014289
    Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: July 19, 2021
    Publication date: January 19, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Giorgio Servalli, Marcello Mariani
  • Publication number: 20230016249
    Abstract: A motor controller comprises a switch circuit and a control unit. The switch circuit is coupled to a motor for driving the motor. The control unit generates a control signal to control the switch circuit. The motor controller determines a non-excitation time. When the motor is in a locked state, the motor controller enables the non-excitation time to be a variable value. The motor controller utilizes the non-excitation time to achieve a lock protection function. The motor controller determines whether the motor is in the locked state by detecting a rotor speed or a rotor temperature. Moreover, the motor controller further comprises a driving signal, where the driving signal has the non-excitation time.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Applicant: Global Mixed-mode Technology Inc.
    Inventor: Ching-Feng Lai
  • Publication number: 20230015330
    Abstract: A method may include positioning one or more PV module mounting devices along a length of a structural component. The method may include specifying one or more parameters related to fastening the PV module mounting devices to the structural component, the one or more parameters indicating a spacing between the PV module mounting devices. The method may include fastening, by an automated attachment equipment, the PV module mounting devices to the structural component based on the specified parameters and moving the PV module mounting devices fastened to the structural component to an assembly platform.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 19, 2023
    Applicant: Array Technologies, Inc.
    Inventors: Nathan Schuknecht, Lucas Creasy
  • Publication number: 20230019413
    Abstract: Disclosed are methods, systems and non-transitory computer readable memory for gesture control. For instance, a system may include a wearable device configured to be worn on a portion of an arm of a user. The wearable device may include a plurality of electrodes disposed on an interior of the wearable device and configured to obtain biopotential signals from the user's arm; and a biopotential chip. The biopotential microchip may be configured to output, directly or indirectly, biopotential data, acceleration data, and/or angular rate data, or derivatives thereof (“gesture data”), to a machine learning classifier. The machine learning classifier may be configured to generate, based on the gesture data, a gesture output indicating a gesture performed by the user. In some cases, the plurality of electrodes may include one or more wristband electrodes and/or a plurality of hub electrodes in a hub. In some cases, the hub may be curved.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Applicant: Pison Technology, Inc.
    Inventors: Kenneth Stern, Tanya Wang, Tristan McLaurin, David Cipoletta, Dexter Ang
  • Publication number: 20230014868
    Abstract: A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple semiconductor pillars, memory structures, and multiple transistors. The multiple semiconductor pillars are arrayed along a first direction and a second direction. Each semiconductor pillar includes a first portion and a second portion on the first portion. The memory structure includes a first electrode layer, a dielectric layer and a second electrode layer. The first electrode layers cover sidewalls of the first portions and are located in first filling regions arranged at intervals. Each first filling region surrounds a sidewall of the first portion. The dielectric layers cover at least surfaces of the first electrode layers. The second electrode layers cover surfaces of the dielectric layers. Channel structures of the transistors are located in the second portions, and extend in a same direction as the second portions.
    Type: Application
    Filed: September 20, 2022
    Publication date: January 19, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Deyuan XIAO, Guangsu Shao, Yunsong Qiu
  • Publication number: 20230014013
    Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.
    Type: Application
    Filed: September 28, 2022
    Publication date: January 19, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
  • Publication number: 20230014320
    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 19, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Yi Fang Lee, Jaydip Guha, Lars P. Heineck, Kamal M. Karda, Si-Woo Lee, Terrence B. McDaniel, Scott E. Sills, Kevin J. Torek, Sheng-Wei Yang
  • Publication number: 20230015046
    Abstract: Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Applicant: Micron Technology, Inc.
    Inventor: Santanu Sarkar
  • Publication number: 20230013727
    Abstract: Disclosed are bone screw drill targeting guides and methods for using such targeting guides that are useful in surgical procedures for correcting hallux valgus deformity.
    Type: Application
    Filed: February 17, 2021
    Publication date: January 19, 2023
    Applicant: WRIGHT MEDICAL TECHNOLOGY, INC.
    Inventors: Zachary KORMAN, Paul LUTTRELL, Joseph Ryan WOODARD, Gary W. LOWERY, Peter George MANGONE
  • Publication number: 20230018059
    Abstract: Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The method includes: providing a semiconductor substrate including a plurality of active pillars arranged at intervals; etching the active pillar to form an annular groove, in which the annular groove does not expose a top surface and a bottom surface of the active pillar; and forming a first semiconductor layer in the annular groove to form the semiconductor structure; in which a band gap of the first semiconductor layer is smaller than a band gap of the active pillar.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 19, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yi TANG
  • Publication number: 20230016806
    Abstract: A method of controlling a skip-fire cylinder deactivation system of an engine system is provided. The method includes a controller deactivating a cylinder of the engine system to operate the engine system in a skip-fire mode. The method further includes determining a temperature of an injector tip nozzle associated with the cylinder and comparing the temperature of the injector tip nozzle to a threshold a temperature. In response to determining that the temperature of the injector tip nozzle is greater than the threshold temperature, the cylinder is activated by the controller.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 19, 2023
    Applicants: CUMMINS INC., TULA TECHNOLOGY, INC.
    Inventors: J. Steven Kolhouse, Ross A. Phillips
  • Publication number: 20230015304
    Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Manuj Nahar, Ashonita A. Chavan
  • Publication number: 20230019887
    Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.
    Type: Application
    Filed: September 28, 2022
    Publication date: January 19, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Akira Yamashita, Kenji Asaki
  • Publication number: 20230013530
    Abstract: A system and method for enforcing a patient's compliance with medicine dosage using an artificial intelligence engine to control a treatment apparatus. A method is disclosed for generating, by an artificial intelligence agent, a dosage compliance plan on a treatment apparatus. The method includes receiving one or more dosage compliance plans that, when applied to one or more users, encourage users to comply with medical prescriptions; receiving data associated with the user, wherein the data comprises at least one modified attribute of the user and at least one attribute of the medical prescription; receiving one or more constraints, wherein the one or more constraints comprises rules pertaining to dosage amounts associated with the one or more dosage compliance plans; and generating, via an artificial intelligence engine, an optimal dosage compliance plan for the user comprising the at least one modified attribute of the user associated with the at least one attribute of the medical prescription.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 19, 2023
    Applicant: ROM TECHNOLOGIES, INC.
    Inventor: Steven Mason