Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. A lower of the first tiers comprises sacrificial material. A horizontally-elongated slot is formed through the first and second tiers to the sacrificial material in individual of the memory-block regions to form laterally-spaced sub-block regions in the individual memory-block regions. The sacrificial material is isotropically etched from the lower first tier through the horizontally-elongated slots.

Abstract: A semiconductor structure includes a base, a dielectric layer, a gate structure, and a covering layer. The base includes discrete semiconductor pillars. The semiconductor pillars are disposed at the top of the base and extend in a vertical direction. The dielectric layer covers the sidewall of the semiconductor pillar. The gate structure is disposed in the middle area of the semiconductor pillar. The gate structure includes a gate-all-around structure, the gate-all-around surrounding the semiconductor pillar. A first part of the dielectric layer is disposed between the gate structures and the semiconductor pillars. The covering layer covers the top of the semiconductor pillar and part of the sidewall close to the top. The material of the covering layer includes a boron-containing compound.

Abstract: A compilation method includes: receiving a signal to be compiled and a working frequency signal; performing compilation processing on the signal to be compiled to obtain a compilation result signal; and if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the working frequency signal to determine a first compilation value.

Abstract: An impedance calibration circuit, an impedance calibration method, and a memory are provided. The impedance calibration circuit includes a parameter module, an initial value generation module, and a calibration module. The parameter module is configured to perform environment detection processing and output an environment parameter signal; the initial value generation module is configured to receive the environment parameter signal, and output an initial calibration value based on the environment parameter signal when the calibration instruction signal is received; and the calibration module is configured to receive the initial calibration value, and perform impedance calibration processing based on the initial calibration value when the calibration instruction signal is received.

Abstract: A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple first active pillars above the substrate, a memory structure, multiple transistors, and multiple second active pillars. The multiple first active pillars are arranged in an array along a first direction and a second direction. The substrate includes an isolation structure on which the first active pillars are located. The memory structure includes first electrode layers, a dielectric layer and a second electrode layer. The first electrode layer covers a sidewall of the first active pillar, the dielectric layer covers at least surfaces of the first electrode layers, the second electrode layer covers a surface of the dielectric layer. Each of the second active pillars is located above a corresponding one of the first active pillars; a channel structure of each transistor is located in the second active pillar.

Abstract: A semiconductor structure includes a plurality memory group provided in rows, each of the memory groups includes a plurality of memories arranged at intervals along a row direction, and for two adjacent ones of the memory groups, the memories in one memory group and the memories in another memory group are staggered.

Abstract: A device for detecting infrared radiation emanating from a subject while not in physical contact with the subject.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.

Abstract: Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a first isolation trench located in the substrate, a first insulating layer covering a bottom surface and a lower part of a sidewall of the first isolation trench, a second insulating layer covering an upper part of the sidewall of the first isolation trench, and a third insulating layer at least partially located between the first insulating layer and the second insulating layer to isolate the first insulating layer from the second insulating layer.

Abstract: A user device is caused to display a visual attribute representation for a plurality of visual attributes. Each visual attribute is based at least in part on an image and each visual attribute representation is selectable. A processor is caused to identify a plurality of items, each item is associated with a visual attribute matching at least one of the plurality of visual attributes. The items are classified a first set and a second set. The items in the first and second sets are mutually exclusive and simultaneously displayed. If the processor receives a single selection of a first visual attribute representation of a first visual attribute of the plurality of visual attributes, the first set consist of items associated with a visual attribute matching the first visual attribute and the second set comprise items associated with a visual attribute matching at least one of the plurality of visual attributes.

Abstract: A receiver includes the following: a signal receiving circuit, including a first MOS transistor and a second MOS transistor, where a gate of the first MOS transistor is configured to receive a reference signal and a gate of the second MOS transistor is configured to receive a data signal, and the signal receiving circuit is configured to output a comparison signal, the comparison signal being configured to represent a magnitude relationship between a voltage value of the reference signal and a voltage value of the data signal; and an adjusting circuit, including a third MOS transistor, where a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to a drain of the first MOS transistor, and a gate of the third MOS transistor is configured to receive an adjusting signal.

Abstract: A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

Abstract: A storage node of a database replica group may distribute different portions of data in local storage and external storage, where local storage and external storage are organized using different types of index structures. Responsive to receiving an access request for a database, a storage node may determine that an item of the database to be accessed by the request does not reside within a first portion of the database stored locally at the storage node. Responsive to this determination, the storage node may obtain from an external storage service a second portion of the database, the second portion including a plurality of items including the item, and the second portion organized according to a structure different from the first portion. The storage node may then store the plurality of obtained items in the first portion and process the request using the first portion of the database.

Abstract: Computer systems and associated methods are disclosed to implement a decision model auditing system that allows clients of a machine learning decision system to audit the decision-making process the decision system. In embodiments, the decision system is instrumented with reporting code to collect internal decision data of the decision system and send the data to a decision auditing service. In embodiments, the auditing service provides the client with an obfuscated token, which may be used to anonymize the client requests to the decision system. As client requests are handled by the decision system, the reporting code generates audit messages to the auditing service. The auditing service stores the audit information, which may later be provided to the client or used generate an audit report. In embodiments, the audit report may indicate whether the decision system contains any undesired bias.

Abstract: The present disclosure relates to a neural network image identification system and a neural network building system and method used therein. The neural network building method comprises: forming a combination sequence of instruction graphic tags according to a plurality of instruction graphic tags selected by a user and displayed on a screen; combining a plurality of program sets corresponding to the plurality of instruction graphic tags in an order identical to that of contents in the combination sequence of these instruction graphic tags, to generate a neural network program; and checking whether the combination sequence of instruction graphic tags conforms to one or more preset rules before the neural network program is compiled.

Abstract: A processing device in a memory system identifies, while the memory device is in a first state condition, a plurality of workload conditions associated with the memory device, wherein the plurality of workload conditions comprise data reflecting a performance condition of the memory device. The processing device determines, while the memory device is in the first state condition, a host rate of a host system write performance for the memory device based on one or more workload conditions of the plurality of workload conditions. The processing device determines that one or more workload conditions of the plurality of workload conditions satisfies a first threshold criterion. Responsive to determining that the one or more workload conditions of the plurality of workload conditions satisfies the first threshold criterion, the processing device detects a change in a condition of the memory device from the first state to a second state.

Abstract: A system may include a processor and a memory. The memory may include computer-executable code that, when executed by the processor, causes the processor to retrieve a workflow dataset from a database based on a query input associated with an industrial automation device. The workflow dataset may include an instruction associated with one or more operations for the industrial automation device and a virtual object associated with the one or more instructions and the industrial automation device. The memory may include computer-executable code that, when executed by the processor, causes the processor to transmit a first portion of the workflow dataset to a computing device corresponding to a first instruction. The memory may include computer-executable code that, when executed by the processor, causes the processor to transmit a second portion of the workflow dataset to the computing device in response to determining that the first instruction is completed.

Abstract: At a first compute instance run on a virtualization host, a local instance scaling manager is launched. The scaling manager determines, based on metrics collected at the host, that a triggering condition for redistributing one or more types of resources of the first compute instance has been met. The scaling manager causes virtualization management components to allocate a subset of the first compute instance's resources to a second compute instance at the host.

Abstract: A storage system comprises a non-volatile memory configured to store boot code and a control circuit connected to the non-volatile memory. In response to a first request from a host to transmit the boot code, the storage system commences transmission of the boot code to the host at a first transmission speed. Before successfully completing the transmission of the boot code to the host at the first transmission speed, it is determined the boot code transmission has failed. Therefore, the host will issue a second request for the boot code. In response to the second request for the boot code, and recognizing that this is a fallback condition because the previous transmission of the boot code failed, the storage apparatus re-transmits the boot code to the host at a lower transmission speed than the first transmission speed.

Abstract: Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices may use an address scrambler to determine a bit error rate for accessing memory cells and remap an address of a particular memory cell to have a bit error rate below a threshold. In this way, the address scrambler may distribute the bit error rates of multiple accesses of the array.