Abstract: A staggering signal generation circuit includes a pulse generation circuit, a counting circuit and a signal generation circuit. The pulse generation circuit generates a first periodic pulse signal and a second periodic pulse signal; the counting circuit counts the first periodic pulse signal and the second periodic pulse signal to generate rising edge triggering signals and falling edge triggering signals; and the signal generation circuit generate a staggering pulse signal according to the input rising edge triggering signals and the input falling edge triggering signals.

Abstract: A motor controller comprises a switch circuit and a control unit. The switch circuit is coupled to a motor for driving the motor. The control unit is configured to generate a control signal to control the switch circuit. The motor controller is configured to generate a current signal and a voltage signal. When a current phase of the current signal is at a predetermined crossing phase, the motor controller calculates a difference value between the current phase of the current signal and a voltage phase of the voltage signal, where the motor controller is configured to control the difference value. The motor controller may stabilize the motor and avoid noise by modulating the difference value. The motor controller may modulate the difference value, such that the difference value is equal to a predetermined phase difference.

Abstract: The present disclosure generally relates to modifying support security parameters without stalling data transfer. Rather than stalling the data transfer when support security modification requests are received. The disclosure proposes incorporating multiple security partition slots in the device controller. Each slot holds security parameters and an IO counter that holds the current number of pending commands in the device that are going to use that slot. The security partition slots are used as ping-pong buffers allowing the device to modify a second slot while freezing the values on a first slot until completing the previous queued commands that are still under execution. The slots allow support security parameter on-the-fly modifications without stalling any IO traffic. The slots feature is very important for QoS and system performance.

Abstract: A method and system for converting database applications into blockchain applications is disclosed. Multiple applications on different nodes can automatically perform global data consensus to prevent data conflicts using the embodiments described. One method involves monitoring databases as they is modified by database applications, to extract data operations from transaction logs, convert the data operations to a general format, and activate the smart contract on the blockchain to complete the data consensus check at multiple nodes. Each node monitors the blocks on blockchain and synchronizes the data back to database. In the case of conflicting data, the data is not able to pass consensus and synchronize with the other nodes in the blockchain. The local nodes automatically roll back when detecting invalid data.

Abstract: A semiconductor structure includes: a substrate, a first gate structure, and a second gate structure. The substrate includes: discrete first semiconductor pillars arranged at a top of the substrate and extending in a vertical direction; and a second semiconductor pillar and a third semiconductor pillar extending in the vertical direction, the second and third semiconductor pillars are provided at a top of each first semiconductor pillar. The first gate structure is arranged in a middle region of the first semiconductor pillar and surrounds the first semiconductor pillar. The second gate structure is arranged in a middle region of the second semiconductor pillar and of the third semiconductor pillar, and includes a first ring structure and a second ring structure. The first ring structure surrounds the second semiconductor pillar, and the second ring structure surrounds the third semiconductor pillar.

Abstract: A layout structure of an anti-fuse array at least includes an array circuit area and a functional circuit area. The array circuit area is electrically connected with the functional circuit area. The functional circuit area is located on at least one side of the array circuit area, and at least one side of the array circuit area is located on an edge of the layout structure. The array circuit area includes an anti-fuse array composed of anti-fuse cells, and the array circuit area is configured to provide the anti-fuse cells under different column addresses to the functional circuit area. The functional circuit area is configured to fuse the anti-fuse cells under the different column addresses.

Abstract: Memory circuitry comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Charge-passage material is in the conductive tiers laterally-outward of the channel-material strings. Storage material is in the conductive tiers laterally-outward of the charge-passage material. At least one of AlOq, ZrOq, and HfOq is in the conductive tiers laterally-outward of the storage material. At least one of (a) and (b) is in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where, (a): MoOxNy, where each of “x” and “y” is from 0 to 4.0; and (b): MoMz, where “M” is at least one of W, a Group 7 metal, and a Group 8 metal; “z” being greater than 0 and less than 1.0. Metal material is in the conductive tiers laterally-outward of the at least one of the (a) and the (b). Memory cells are in individual of the conductive tiers.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The method for manufacturing the semiconductor structure includes: a substrate is provided: a plurality of semiconductor channels arrayed in a first direction and a second direction are formed on the substrate: a plurality of bit lines extending in the first direction are formed, in which the bit lines is located in the substrate: and a plurality of word lines extending in the second direction are formed, in which two word lines adjacent to each other in the first direction are spaced apart from each other in a direction perpendicular to a surface of the substrate: and a sidewall conductive layer is formed, in which the sidewall conductive layer is located above one of the two word lines adjacent to each other, and is arranged in the same layer as the other of the two word lines.

Abstract: A semiconductor structure, a method for manufacturing a semiconductor structure, and a memory are provided. The semiconductor structure includes: a source and a drain which are arranged in a substrate; a gate dielectric layer arranged in the substrate and covering a sidewall and a bottom portion of a trench defined between the source and the drain; a gate structure arranged in the trench, in which a material of the gate structure includes metal or metal compound; and a gate adjustment layer at least arranged between the gate dielectric layer and the gate structure. A sidewall of the gate structure is provided with a first control area covered with the gate adjustment layer, and a bottom surface of the gate structure is provided with a second control area not covered with the gate adjustment layer. A material of the gate adjustment layer includes polycrystalline silicon.

Abstract: A method for forming a semiconductor structure includes the following: providing a semiconductor substrate, in which stack structures and isolation structures alternately arranged along a first direction are formed on the semiconductor substrate; forming a support structure in the stack structures and the isolation structures; etching the stack structures and the isolation structures to form multiple zigzag first semiconductor pillars in an array arrangement along the first direction and a second direction, in which an interspace is formed between the zigzag first semiconductor pillars; each zigzag first semiconductor pillar comprises first convex structures and first concave structures alternately arranged along a third direction, and is supported by the support structure; the first direction, the second direction and the third direction are perpendicular to one another, and the second direction is perpendicular to a top surface of the semiconductor substrate; forming capacitor structures the interspace.

Abstract: An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

Abstract: Embodiments of the present invention provide a method for manufacturing a semiconductor structure, which includes: a base is provided and a stack layer is formed on the base, wherein the stack layer includes at least a first sacrificial layer, and a material of the first sacrificial layer includes an amorphous elemental semiconductor material; second hard mask patterns are formed on the first sacrificial layer through a self-aligned process; a doping process is performed, which includes the operation that a region of the first sacrificial layer exposed from gaps between the second hard mask patterns is doped; the second hard mask patterns are removed; and an undoped region of the first sacrificial layer is removed through a selective etching process so as to form first sacrificial patterns.

Abstract: Devices and methods are provided for filtering contaminants or pollutants from water, such as rainwater or stormwater. The devices include a liquid filter comprising a tubular mesh enclosure containing a filling. The filling comprises compost particles and an activated carbon material. The compost particles have a bulk particle distribution of more than 30% less than 0.375 inches and at least 90% less than 2 inches. This unique combination of particle sizes and filling materials increases the removal efficiency of the filter. In addition, this filter media absorbs a broader range of industrial pollutants than conventional filters.

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.

Abstract: Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor structure includes a base in which a first doped region is provided and an active pillar group arranged in the first doped region. The active pillar group includes four active pillars arranged in an array. At least one of the active pillars is provided with a notch, which faces at least one of a row centerline or a column centerline of the active pillar group.

Abstract: Methods of forming a transistor might include removing portions of a semiconductor to define a semiconductor fin having an upper portion having an uppermost surface at a first level and extending from the first level to a second level, and a lower portion, wider than the upper portion, having an uppermost surface at the second level and extending from the second level to a third level; forming first and second isolation regions at the third level and adjacent the lower portion of the semiconductor fin; forming a first dielectric overlying portions of the semiconductor that are lower than a level between the first level and the second level; forming a second dielectric overlying an exposed portion of the upper portion of the semiconductor fin; forming a conductor overlying the second dielectric; and forming first and second source/drains in the lower portion of the semiconductor fin at the second level.

Abstract: A method is disclosed for rejuvenation a cobalt Fischer Tropsch catalyst used in a Fischer Tropsch process operating in recycle mode. The method permits the use of specific inert gases to adjust the mole weight of the gas so that the recycle compressor designed for normal steady state operation can also be used in the method. Hydrogen from a membrane permeate stream is added to the reactor loop at a temperature between 300 F and 400 F and the carbon oxides are reacted out to purify the hydrogen. This stream is continuously recycled and the temperature is raised to between 425 F and 500 F and held at the final temperature for between 4 hours and 48 hours. The cobalt Fischer Tropsch catalyst is effectively rejuvenated in-situ by the method.

Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.