Abstract: A system and method of electronic health record data qualification is presented. A Qualification List can be used in the practical application of data qualification that uses a predefined list of data to determine if the current values of input fields, which correspond to properties of the predefined list, match any item in the list according to the value of a ‘compare mnemonic’ (e.g., EQ, NE, GT, LT, GE, LE) of the corresponding input field. The system can advantageously override established processing flows by inverting determination values to direct the processing of the acquired data. Advantageously, the system can provide context for the values by retrieving data within an execution context, thereby acting as a gatekeeper to direct subsequent processing.

Abstract: Leveraging wireless direct transmissions may be provided. It may be determined that data traffic flowing on a first pathway between a first client device and a second client device is not meeting a predetermined service level. The first pathway may be partially wired and partially wireless. A second pathway that will meet the predetermined service level may be determined. The second pathway may be wireless. The data traffic may be caused to flow on the second pathway.

Abstract: A heat-assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) with an output tip at the GBS and a main magnetic pole with a pole tip at the GBS. The pole tip has a narrow cross-track width that can be substantially the same as the cross-track width of the NFT output tip. A plasmonic layer is located between the main pole and the NFT and has a tip at the GBS between the main pole tip and the NFT output tip. The plasmonic layer may also be located on the cross-track sides of the main pole and the main pole tip.

Abstract: The present disclosure provides an order processing system is disclosed, comprising an order receiving unit that receives and indexes orders based on order specifications. The system also includes a provider database, which stores a plurality of provider identifier codes (PICs) that are individually associated with a provider, at least one benefit offered by the provider, and the historical credit information of the provider. The benefit determination unit, which is communicably coupled with the order receiving unit and the provider database, receives the order specifications, identifies a preferred PIC for the received order, and determines a credit difference to be adjusted in order to facilitate availing at least one benefit. The benefit determination unit also updates the historical credit information of the provider associated with the identified preferred PIC and facilitates availing the benefit(s) for a customer.

Abstract: Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.

Abstract: There is provided a target-based shortest path extracting method. The method includes recognizing three or more sites within a designated area of a target and setting a start site among the recognized sites; extracting a tree graph by connecting sites within the designated area, starting with the start site; and extracting the shortest path between sites within the designated area of the target by connecting tree lines of the tree graph, starting with the start site.

Abstract: Broadcast energy and spectrum consumption optimization may be provided. It may be determined, by a computing device for each of a plurality of client devices, a corresponding plurality of respective minimum Modulation and Coding Schemes (MCSs) needed to reach each of the respective plurality of client devices from the computing device at a predetermined power level. Next, an optimal MCS from the plurality of respective minimum MCSs may be used to reach a first group of the plurality of client devices via broadcast. Then unicast may be used to reach a second group of the plurality of client devices wherein the optimal MCS is selected to minimize the total amount of airtime used for the broadcast and the unicast.

Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, an assist gate structure, a tunneling dielectric layer, a floating gate, and an upper gate structure. The assist gate structure is disposed on the substrate. The floating gate includes two opposite first top edges arranged along a first direction, two opposite first sidewalls arranged along the first direction, and two opposite second sidewalls arranged along a second direction different from the first direction. The upper gate structure covers the assist gate structure and the floating gate, where at least one of the first top edges of the floating gate is embedded in the upper gate structure. Portions of the upper gate structure extend beyond the second sidewalls of the floating gate in the second direction, and the portions of the upper gate structure are disposed above the substrate.

Abstract: Apparatuses, systems, and methods for input buffer data feedback equalization (DFE). An input buffer includes a DFE circuit which adjusts a threshold voltage of the input buffer based on a previously latched data bit. The DFE circuit includes a number of DFE legs coupled in parallel to a node of the input buffer. Each DFE leg is selectively activated by a DFE code. Each DFE leg includes a capacitance (e.g., a field effect transistor) which is coupled to the node in an active leg based on the previously latched data bit. The previously latched data bit may also be used to generate a reset signal which couples the capacitors to ground. Each DFE leg may also include a transistor coupled to a bias voltage, which is stable across a range of PVT variations.

Abstract: Changes made to a database table are accumulated, in durable storage, and snapshots of partitions of the table are obtained. For successive snapshots of a partition, the system accesses a previous snapshot, applies changes from the accumulated changes, and stores the updated snapshot to a durable data store. The accumulated changes and the successive partition snapshots are made available to restore the database to any point in time across a continuum between successive snapshots. Although each partition of the table may have a backup snapshot that was generated at a time different from when other partition snapshots were generated, changes from respective change logs may be selectively log-applied to distinct partitions of a table to generate an on-demand backup of the entire table at common point-in-time across partitions. Point-in-time restores of a table may rely upon a similar process to coalesce partition snapshots that are not aligned in time.

Abstract: Disclosed techniques enable cluster-based dynamic content with multi-dimensional vectors for video content analysis. User-specific data vectors on a plurality of users are accessed, which include shopping history and video consumption behavior. A plurality of clusters, based on the user-specific data vectors, is developed. A user, from the plurality of users, is associated with one or more clusters from the plurality of clusters. The user is identified as viewing media content. A container unit is inserted into the media content that is being viewed and is populated with at least one short-form video from a library of short-form videos. The populating is based on the identifying. An ecommerce purchase of a product for sale to the user is enabled. The product for sale is relevant to the one or more clusters and the at least one short-form video. The ecommerce purchase is accomplished within a short-form video window.

Abstract: Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

Abstract: Systems and methods described herein support enhanced computer vision capabilities which may be applicable to, for example, autonomous vehicle operation. An example method includes generating a latent space and a decoder based on image data that includes multiple images, where each image has a different viewing frame of a scene. The method also includes generating a volumetric embedding that is representative of a novel viewing frame of the scene. The method includes decoding, with the decoder, the latent space using cross-attention with the volumetric embedding, and generating a novel viewing frame of the scene based on an output of the decoder.

Abstract: Technology is disclosed for testing a 3D memory structure. The 3D memory structure has blocks with layers of word lines. Each word line is connected to control gates of NAND memory cells. The 3D memory structure may be tested while concurrently applying a set of layer dependent voltages to a corresponding set of word lines. The magnitude of each layer dependent voltage may depend on which layer the word line to which the voltage is applied resides. There may be physical differences between the different layers such as differences in the diameters of the memory holes in which NAND string are formed. The layer dependent voltages provide for a more accurate test in view of these and other physical differences between the different layers.

Abstract: Disclosed herein are methods and systems for automatically validating evidence of traffic violations. One instance of a method comprises receiving an evidence package comprising video frames showing a vehicle involved in a potential traffic violation. The video frames can be input into one or more deep learning models to obtain a plurality of classification results. The method can further comprise generating a score based in part on the classification results and evaluating the score against one or more thresholds to determine whether the evidence package is automatically approved, is automatically rejected, or requires further review.

Abstract: Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Abstract: Disclosed embodiments integrate jurisdictionally compliant smart contract formation, the fusion of automated transactions with professional services interfaces, and the ability to handle the complexities of modern commerce within a decentralized framework. Disclosed systems may include multiple blockchain storage of hashed data sets during the formation and negotiation of smart contracts with integrated asset verification and digital wallet creation and use. Disclosed embodiments include a comprehensive ecosystem that ensures security, transparency, ease of verification and robustness tailored for contemporary business needs.

Abstract: Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.