Abstract: Devices and techniques are generally described for wake word suppression using variable step size of an acoustic echo cancellation (AEC) unit. A reference signal representing an audio stream may be sent to an acoustic echo cancellation (AEC) unit. A microphone may receive an input audio signal and send the input audio signal to the AEC unit. The AEC unit may determine a first set of variable step size (Vss) values over the first time period. Vss values may define a rate at which the AEC unit determines a transfer function between the reference signal and the first input audio signal. A wake-word may be detected during the first time period. A determination may be made that the wake-word is part of the audio output by the loudspeaker based at least in part on the first set of Vss values.

Abstract: A process for separation of a slurry by radially injecting a stream of a nanogas solution at a shear-focus volume within a pipe; passing an aqueous slurry through the pipe along a direction of flow and through the shear-focus volume; and shearing and/or admixing the slurry with the nanogas solution within the shear-focus volume.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, having a first region and a second region; a first gate structure positioned in the first region and a second gate structure positioned in the second region, the first gate structure being a high dielectric constant gate including a first gate electrode layer and a high dielectric constant layer, and the second gate structure including a second gate electrode layer and an oxide insulating layer; a spacer and an interlayer dielectric layer, positioned on the first gate structure and the second gate structure, the spacer and the interlayer dielectric layer covering a part of the second gate structure, the substrate, and the first gate structure; and a second contact plug, penetrating through the spacer and the interlayer dielectric layer and being in contact with the substrate.

Abstract: The present disclosure provides a voltage generating circuit and a memory. The voltage generating circuit includes: a voltage output module configured to receive a reference voltage, generate a first output voltage, and provide the first output voltage to a power supply node, where the power supply node is connected to a load to supply power to the load; a voltage stabilizing module configured to receive the reference voltage and generate and output a control signal; and a compensation module configured to receive a power voltage, a flag signal and the control signal, be turned on in response to the flag signal, and configured to provide a second output voltage to the power supply node in response to a voltage value of the control signal, such that a voltage of the power supply node is recovered to the first output voltage.

Abstract: A DRC test pattern generation method includes: receiving a DRC test pattern generation request, the DRC test pattern generation request carrying the number of correct patterns and the number of erroneous patterns; acquiring layout design rule information and corresponding layer configuration information, the layer configuration information including process layer configuration parameter information that is set according to a process type; parsing parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the layer configuration information, and generating formatted parameter information corresponding to the each rule; and generating a corresponding number of correct patterns and a corresponding number of erroneous patterns corresponding to each rule according to the formatted parameter information.

Abstract: An amplifier includes a first and a second differential input ports, and a single-ended output port. The amplifier includes a first and a second transistors, each having a gate, source, and drain terminals. The source terminals are coupled to a reference plane and the gate terminals are coupled to the respective first and second differential input ports. The amplifier includes a Balun having a primary and a secondary transformer winding, the primary transformer winding having one end coupled to the drain terminal of the first transistor, an opposite end coupled to the drain terminal of the second transistor, and a center tap coupled to a bias voltage, and the secondary transformer winding is adjacent to the primary transformer winding and having one end coupled to the single-ended output port and an opposite end open circuited. An electromagnetic field generated at the primary induces a signal at the secondary transformer winding.

Abstract: A radiation detector unit includes a read-out integrated circuit (ROIC) including a plurality of core circuit blocks located on a continuous uninterrupted substrate adjacent to one another along a first direction, and a plurality of radiation sensors bonded to a front side surface of the ROIC, where each radiation sensor of the plurality of radiation sensors is bonded to a respective core circuit block of the plurality of core circuit blocks of the ROIC. Additional embodiments include detector modules and detector arrays formed by assembling the detector units, and methods of operating and manufacturing the same.

Abstract: A maintenance bag of an ostomy system can include fewer sensors than a diagnostic or analytic ostomy bag that is typically used for newer users. The maintenance bag can include sensors and electronics to detect fill level of the bag. The maintenance bag can also include a bag sealing mechanism that can detect drainage events and aid the user to track inventory of the bags. A wafer that can be used with an ostomy bag can include leak sensors configured to detect leak of effluent. The wafer can also include temperature sensors configured to detect inflammation. The wafer can further include a convex interface for better fit with certain users.

Abstract: A method for fabricating a custom cranial remodeling device for correction of cranial deformities in a subject is described. The method comprises generating a three-dimensional head data file for the subject and determining contour lines on the head. The method further comprises automatically generating a modified head shape data file. Still further the method includes utilizing the modified head shape data file to generate a shape for a desired custom cranial remodeling device and restricting growth of the head in first areas.

Abstract: A process for printing a talus implant comprising the steps of scanning a joint for a damaged talus, and scanning a contralateral joint for a healthy talus. Next, the process includes obtaining dimensions for a talus based upon an initial scan and then obtaining dimensions for a talus based upon the scan of the contralateral joint. Next the process includes inverting the dimensions of the talus in the contralateral joint and then comparing the dimensions of the calculated talus with a pre-set of dimensions in a database. Next the process includes exporting a set of dimensions to a printer to print a talus implant.

Abstract: A method for fabricating a custom cranial remodeling device for correction of cranial deformities in a subject is described. The method comprises generating a three-dimensional head data file for the subject and determining contour lines on the head. The method further comprises automatically generating a modified head shape data file. Still further the method includes utilizing the modified head shape data file to generate a shape for a desired custom cranial remodeling device and restricting growth of the head in first areas.

Abstract: A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure at least includes two photolithography layers which are arranged in sequence and at least one blocking layer. Each photolithography layer includes a functional pattern and an overlay mark, and the photolithography layers include a first photolithography layer and a second photolithography layer. The first photolithography layer includes a first functional pattern and a first overlay mark, and the second photolithography layer includes a second functional pattern and a second overlay mark; and at least one blocking layer. The blocking layer is located between the first functional pattern and the second functional pattern, and a vertical distance between the first functional pattern and the second functional pattern is greater than a vertical distance between the first and second overlay marks, in a stacking direction of the photolithography layers.

Abstract: A device comprises a display and a plurality of radars. For example, the radars may be arranged around a perimeter of the device, with their respective fields of view directed toward the display. Output from the radar is processed to generate input frames. The input frames are then processed to determine touch data indicative of a position with respect to the display. The input frames may be processed to determine the touch data using a trained machine learning module or a geometric estimation module. For example, the trained machine learning module may accept input frames comprising one or more of range fast-Fourier transform (FFT) data or doppler FFT data and provide as output the touch data.

Abstract: Methods for transmitting asynchronous event data via synchronous communications interfaces (and associated imaging systems) are disclosed herein. In one embodiment, an imager comprises an array of event vision pixels, and a synchronous communications transmitter configured to transmit frames of data to a synchronous communications receiver. The pixels generate event data based on activity within an external scene. The imager communicates, at a first time and to the receiver, an anticipated amount of data that will be included in a frame transmitted to the receiver at a second time. The anticipated amount of data can be based on a prediction of an amount of event data that will be generated at a future point in time for transmission to the receiver in the frame. The imager can then transmit the frame to the receiver at the second time with an amount of data corresponding to the anticipated amount of data.

Abstract: Integrated vehicle structures are provided herein. An integrated vehicle structure can include an enclosure portion configured to house an electric motor and a plurality of extended portions extending from the enclosure portion. The enclosure portion and the plurality of extended portions can be load-bearing and configured to bear vehicle loads. The extended portions of the integrated vehicle structures can include a connection portion configured to connect with another load-bearing structure to at least receive or transmit loads. The plurality of extended portions can be configured to transfer vehicle loads along physically separate paths. A portion of the enclosure portion can define an opening configured to allow a drive shaft to connect the electric motor to a wheel. The enclosure portion can be configured with an opening for allowing the installation and removal of the electric motor.

Abstract: Embodiments of the present disclosure disclose a lithography method, a lithography apparatus, and a computer storage medium. The method includes: determining an exposure intensity of a mask aligner; determining a target preset interval corresponding to the mask aligner according to the exposure intensity; determining, according to the target preset interval, at least one target wafer for which at least one exposure dose is a target exposure dose, the target preset interval has a corresponding relationship with the target exposure dose; and performing lithography process on the at least one target wafer by using the mask aligner.

Abstract: A pixel array includes pixel circuits including a first pixel circuit having a first split floating diffusion receiving charge from first and third photodiodes through first and third transfer transistors, and a second split floating diffusion receiving the charge from second and fourth photodiodes through second and fourth transfer transistors. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits.

Abstract: A method for determining bone mass density (BMD) of a patient includes obtaining X-ray scan data of a region of interest (ROI) of the patient using an energy discriminating photon counting radiation detector, and calculating the bone mass density (BMD) of the region of interest of the patient based on detected X-ray photon counts within three or more energy bins.