Abstract: Embodiments of the present disclosure provide a method and an apparatus of testing a word line. After repair of a memory array is completed, if a target word line in a failure state exists in the memory array, a second numerical value is written into the target word line, and then it is determined, according to a numerical value outputted by each word line in the memory array, whether there are at least two word lines in an on-state in the memory array; if there are at least two word lines in an on-state simultaneously in the memory array, a current value generated by the target word line in an on-to-off process is detected; when the current value generated by the target word line in the on-to-off process is greater than a preset current threshold, it is determined that the target word line has a repair fault.

Abstract: The present disclosure relates to a computer-implemented method for controlling access to user data of a user. The method comprises: receiving, by a data controller, an access request requesting access to the user data; determining, by the data controller, a consent status and one or more item of information associated with the user data; encrypting, by the data controller, the user data in an encrypted data package encrypted based on the consent status and one or more item of information; and sending, by the data controller, the encrypted data package in response to the access request.

Abstract: Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.

Abstract: A method and system of supplementing a main illuminating light with a supplementary illuminating light using a plurality of solid-state light emitters to illuminate a space according to a target illumination spectrum are provided. The method can include determining or receiving a reference illumination spectrum associated with the main illuminating light. The method can also include determining a spectral deviation between the reference illumination spectrum and the target illumination spectrum. The method can further include controlling the solid-state light emitters to emit respective emitter beams forming the supplementary illuminating light and illuminating the space along with the main illuminating light, the emitter beams having respective emitter spectra together defining a supplementary illumination spectrum of the supplementary illuminating light.

Abstract: A repair system and a repair method for a semiconductor structure, a storage medium, and an electronic device are provided. The semiconductor structure includes a main memory area and a redundant memory area. The repair system of the present disclosure includes a test circuit, a control circuit, and a repair circuit. The test circuit is configured to perform defect detection on the main memory area to determine a failed cell of the main memory area and position information of the failed cell. The control circuit is connected to the test circuit, and is configured to store the position information of the failed cell and generate a repair signal according to the position information. The repair circuit is connected to the control circuit, and is configured to receive the repair signal and perform a repair operation on the failed cell through the redundant memory area.

Abstract: Systems and methods for advertisement-based vehicle matching and routing. For example, a computer-implemented method includes obtaining data associated with a vehicle service request. The data associated with the vehicle service request is indicative of a pick-up location and a destination location associated with the vehicle service request. The method includes determining, from among a plurality of candidate vehicles, a selected vehicle for the vehicle service request based on the data indicative of the vehicle service request, candidate advertisement content items, and candidate routes for the plurality of candidate vehicles. The method includes communicating data that initiates display of a selected advertisement content item by a display device positioned on an exterior of the selected vehicle. The method includes communicating data indicative of route information to a computing device associated with the selected vehicle. The route information includes a selected route to the pick-up location.

Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.

Abstract: A joint training network including a multi-heard module comprising a network input, a feature network coupled to the network input and including a feature detector decoder outputting interest points and a descriptor generator decoder outputting descriptors, the feature detector decoder and the descriptor generator decoder coupled in parallel, a depth network including a monocular depth prediction decoder and outputting a depth map, a flow network including an image segmentation decoder and outputting a segmented image, a segmentation network including a warping module outputting a rotation and translation and an input warp signal to a segmentation decoder outputting a residual flow and a pose network including a fully connected pose estimator coupled to an adder that receives input from the pose estimator and the residual flow from the segmentation decoder, the adder outputting an optical flow.

Abstract: Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

Abstract: A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performing a first error correction code encoding processing on the first data, and transmit second data to a memory die in the writing phase, wherein the second data includes a first data after the first error checking and correction processing; the base die is further configured to receive the second data from the memory die in a reading phase, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading phase, wherein the third data includes the second encoded data and the first data after the first error checking and correction processing.

Abstract: A layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory are provided. The layout of the delay circuit unit includes multiple layout units arranged in an array and each forming a NOT-AND (NAND) gate circuit; here several layout units conforming to a first layout pattern are sequentially arranged in a first row of the array; and several layout units conforming to a second layout pattern are sequentially arranged in a second row of the array; here the first layout pattern is different from the second layout pattern, and the first layout pattern and the second layout pattern are such that the first row and the second row form a center-symmetrical structure.

Abstract: Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

Abstract: A motor control center includes an enclosure comprising an isolation switch, a main contactor device, and a ground switch device. The isolation switch is selectively manually operable between a connected state and a disconnected state. In the connected state the isolation switch is adapted to conduct electrical power from an associated power source to the main contactor device and wherein the isolation switch in the disconnected state interrupts conduction of electrical power from the associated power source to the main contactor device.

Abstract: Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.

Abstract: The present application discloses a semiconductor structure. The semiconductor structure includes: a substrate, the substrate being provided with a conductive structure; a first lower electrode and a second lower electrode sequentially stacked, the first lower electrode being located between the second lower electrode and the substrate, and the first lower electrode being electrically connected to the conductive structure; a first dielectric layer and a first upper electrode, the first dielectric layer covering a sidewall surface of the first lower electrode, and the first upper electrode being located on one side of the first dielectric layer away from the first lower electrode; and a second dielectric layer and a second upper electrode, the second dielectric layer covering an inner wall and a bottom surface of the second lower electrode, and the second upper electrode filling the recess of the second lower electrode.

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first bit line extending in a first direction, a first sense amplifier configured to amplify a potential of the first bit line, and a first transistor configured to supply an operation voltage to the first sense amplifier when a first control signal supplied to a gate electrode of the first transistor is activated. The first wiring layer further includes a first pattern coupled to the gate electrode of the first transistor and a second pattern having a first section arranged between the first bit line and the first pattern in a second direction perpendicular to the first direction.

Abstract: Embodiments of the present application relate to the field of semiconductor manufacturing technologies, in particular to a semiconductor structure and a mask plate structure. The semiconductor structure includes a substrate, where the substrate is provided therein with active areas and a plurality of bit line structures arranged at intervals in parallel in the substrate. A plurality of word line structures are arranged at intervals in parallel in the substrate. The word line structures and the bit line structures intersect to define a plurality of grids arranged in an array on the substrate. Capacitor plugs are located in the grids. Projection of each of the capacitor plugs on the substrate covers a part of one of the active areas. Cross sections of the capacitor plugs are arcuate in a cross section parallel to a surface of the substrate.

Abstract: The disclosure relates in some aspects to a design for a data storage apparatus with a non-volatile memory that includes a block of memory comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a failure in a first sub-block. The second sub-block is then marked, in response to a failure detection in the first sub-block, with an initial designation as an unusable sub-block, and a test of the second sub-block is performed to determine a usability of the second sub-block. Based on the test, the second sub-block is then marked with a second designation that is one of a tested usable sub-block or a tested unusable sub-block.

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.

Abstract: A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.