Abstract: Storage units including platforms that are outfitted with RFID antennas and auxiliary sensors detect changes in loading on the platforms based on changes in loading determined by the auxiliary sensors or changes in signals received by the RFID antennas. The platforms include surfaces for receiving items tagged with RFID transmitters thereon, such as items of common types and variable weights. An interaction involving the placement of an item on the platform, or the removal of the item from the platform, is detected by the auxiliary sensors. The energization of an RFID field is triggered in response to the detected interaction, and an item is identified where an RFID signal transmitted by the item is present at one time and absent at another time.

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

Abstract: Implementations described herein relate to memory device operations for unaligned write operations. In some implementations, a memory device may receive, from a host device, a write command indicating data having a first size that corresponds to a first write unit and a first logical address. The memory device may allocate a set of buffers for the write command. The memory device may determine a set of physical addresses corresponding to a physical address that is associated with the second size, where the set of physical addresses are each associated with the first size. The memory device may merge stored data from the set of physical addresses to one or more buffers, from the set of buffers, that do not include the data to generate a data unit having the second size. The memory device may write the data unit to memory indicated by the set of physical addresses.

Abstract: A network device has a first OS component, a second OS component is added to run concurrently with the first. The first OS component transmits routing information to the second OS component where it is stored in memory. The second OS component registers with a routing infrastructure to receive packets that are routed to the first OS component. A timestamp and a first ID are added to a first instance of a packet and transmitted to the first OS component. The timestamp and a second ID are added to a second instance of the packet and transmitted to the second OS component. First functionality data for the first OS component is transmitted to a controller. Second functionality data for the second OS component is transmitted to the controller. The first and second functionality data are compared to determine whether to replace the first OS component with the second OS component.

Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.

Abstract: This disclosure describes a system for automatically transitioning items from a materials handling facility without delaying a user as they exit the materials handling facility. For example, while a user is located in a materials handling facility, the user may pick one or more items. The items are identified and automatically associated with the user at or near the time of the item pick. When the users enters and/or passes through a transition area, the picked items are automatically transitioned to the user without affirmative input from or delay to the user.

Abstract: Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

Abstract: Disclosed techniques generate a data structure including data representing a configuration of a data storage system. A parameter can be obtained that is usable to configure the data storage system. Data representing the configuration of the data storage system can be modified based on the parameter. The data storage system can be configured, using the parameter, based on the modified data representing the configuration of the data storage system and predetermined configuration data for the data storage system.

Abstract: The present application relates to a semiconductor equipment regulation method, including: providing a simulated wafer; placing the simulated wafer in an etching chamber, and conditioning a temperature in the chamber by using a temperature control device while the simulated wafer is etched by using an etching gas; during the etching process, forming a polymer layer on a surface of each etch hole; acquiring a thickness distribution map of the polymer layer in the entire simulated wafer; comparing the acquired thickness distribution map with a target thickness distribution map; and adjusting a temperature control effect through using the temperature control device on each region of the simulated wafer according to a result of the comparison, so as to adjust thickness uniformity of the polymer layer in the entire wafer.

Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.

Abstract: An electrostatic chuck including a workpiece support surface, clamping layer, heating layer, thermal control system, and sealing band is disclosed. The sealing band surrounds an outer perimeter of the electrostatic chuck including at least a portion of the workpiece surface. The sealing band has a width greater than about 3 millimeters (mm) up to about 10 mm. Plasma processing apparatuses and systems incorporating the electrostatic chuck are also provided.

Abstract: Techniques are described for generating transaction data for a transaction, the transaction data generated with varying fidelity levels based on various constraints. In response to a transaction request from a client, a contract engine may perform service call(s) that instruct network service(s) to generate transaction data. The service call(s) may include constraint(s) on the generation of the transaction data, such as a time limit or a requested fidelity. The network service(s) may generate the transaction data at a particular fidelity based on the time limit, requested fidelity, or other criteria such as current load on the network service(s). The transaction data may be communicated to the contract engine with a fidelity indicator. Lower fidelity transaction data may be sent to the client to enable a low latency user experience. The lower fidelity transaction data may subsequently be replaced with higher fidelity transaction data generated with higher latency.

Abstract: Plasma processing apparatus and associated methods are provided. In one example, a plasma processing apparatus can include a plasma chamber configured to be able to hold a plasma. The plasma processing apparatus can include a dielectric window forming at least a portion of a wall of the plasma chamber. The plasma processing apparatus can include an inductive coupling element located proximate the dielectric window. The inductive coupling element can be configured to generate a plasma from the process gas in the plasma chamber when energized with radio frequency (RF) energy. The plasma processing apparatus can include a processing chamber having a workpiece support configured to support a workpiece. The plasma processing apparatus can include an electrostatic shield located between the inductive coupling element and the dielectric window. The electrostatic shield can be grounded via a tunable reactive impedance circuit to a ground reference.

Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.

Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: The present disclosure generally relates to utilizing the host clock signal frequency to determine whether to operate in the default pulse width modulation (PWM) link startup sequence (LSS), be changed to high speed (HS) LSS by a host device capable of operating in either PWM LSS or HS LSS, or ignore the data storage device attributes of operating in PWM LSS and instead operate according to HS LSS. In so doing, the data storage device is adaptable to work with older generation UFS host devices as well as current and future generation UFS host devices.

Abstract: A system is provided for determining which user inputs correspond to eligible actions for a particular device type. The system determines a device type identifier corresponding to the device that receives the user input and an action to be performed in response to the user input. The system determines that the performed action corresponds to an eligible action type for the device type identifier, and performs further processing using data related to the corresponding user input. Different device type identifiers may be associated with different eligible action types. The system may evaluate multiple user inputs from different users and different devices.

Abstract: A method for inputting an image display information is provided, and the method comprises: taking a measurement result image of a measuring device to obtain an output image by a camera of a terminal device; transmitting the output image to a cloud server via a communication interface of the terminal device; and recognizing the output image to obtain a recognized matching result related to a recognized measurement value and a recognized measurement unit; and saving the recognized matching result via the cloud server.