Abstract: Techniques for modeling a part with a complex geometric feature (CGF) for use with a three-dimension (3-D) printer are disclosed. In one aspect of the disclosure, a method of modeling a part for 3-D printing includes determining a first volume of the part. The first volume may be modeled using a 3-D computer-aided design (CAD) model. A second volume of the part is determined. The CGF may be modeled within the second volume using parametric modeling based on 3-D printing parameters.

Abstract: Having a flexible robotic system layout that allows for the assembly of any structure creates a challenge in finding an optimal sequence of assembly. In some examples, the optimal sequence of assembly may provide the highest robot utilization, the shortest cycle time, the greatest assembly accuracy of the final assembly, or any combination thereof. The processing system disclosed herein may be configured to generate assembly sequences for a plurality of parts and determine an optimal assembly sequence from the generated assembly sequences by comparing the generated assembly sequences.

Abstract: A semiconductor structure includes: a core device region and an anti-fuse device region, disposed on a same substrate; a first dielectric layer, disposed on the substrate of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant; a second dielectric layer, disposed on the first dielectric layer of the core device region; and a conductive layer, disposed on the second dielectric layer of the core device region and the first dielectric layer of the anti-fuse device region; wherein the second dielectric layer has a dielectric constant larger than the first dielectric constant.

Abstract: An apparatus for trimming plant material includes a housing having at least one receptacle configured to removably receive at least one cutting reel system to rest unsecured therein. The housing includes a closeable lid having retention structure configured to operably secure the at least one cutting reel system in the at least one receptacle when the lid is closed. In some embodiments, the housing is further configured to removably receive a knife assembly to rest unsecured in the housing, and the retention structure of the closeable lid further includes a knife retention structure configured to operably secure the knife assembly in engagement with the at least one cutting reel system when the lid is closed.

Abstract: A decoding drive circuit includes at least one decoding driver. The decoding driver includes a first-stage drive circuit and a second-stage drive circuit. Herein, the first-stage drive circuit is configured to receive an enabling control signal, a decoding input signal and a drive control signal, and generate a first drive signal and a second drive signal according to the enabling control signal, the drive control signal and the decoding input signal. The second-stage drive circuit is configured to generate a target word line drive signal according to the first drive signal and the second drive signal. Thus, the embodiments of the disclosure provide a new decoding drive circuit.

Abstract: One aspect is an apparatus including a plurality of additively manufactured components each having an adhesive injection channel. The components are connected together such that adhesive injection channels are aligned to form an adhesive path that allows adhesive flow between the components. Another aspect is an apparatus, including an additively manufactured component having an adhesive injection channel and an adhesive flow mechanism comprising at least one of an adhesive side end effector or a vacuum side end effector, the adhesive flow mechanism configured to provide adhesive to the adhesive injection channels.

Abstract: A housing and/or installation frameworks for a modular multi-level energy system includes a set of similar cabinets configured for orthogonal (e.g., vertical and horizontal) alignment of the modules. The cabinets are configured so modules of a particular phase are oriented along an axis parallel to a reference plane. Modules of the same level of the multi-level arrangement but of different phases are mounted in each cabinet, arranged such that a module for each phase is a defined distance from the reference plane. The cabinets are arranged equidistant and orthogonal to the reference plane, minimizing distance for connections between modules of the same phase across multiple cabinets, and facilitating convenient addition or removal of levels. The framework also facilitates data and reference signal connections between local control devices of the modules, and between the local control devices and a master control device for the system.

Abstract: A satellite utilizes a scheduler to manage uplink contention by providing a user terminal (UT) with grants to use uplink resources. The scheduler may process buffer data status (BDS) information received from the UT that indicates data enqueued by the UT for transmission on the uplink. Based on the BDS the scheduler provides solicited grants to the UT. When there is no backlog of enqueued data on the uplink, unsolicited grants (USGs) are provided to the UT. The USGs provide the UT with access to the uplink without resorting to a high latency random-access channel. If the UT utilizes the USG, subsequent USGs may be provided at shorter repetition intervals. If the UT does not utilize the USG, subsequent USGs may be provided at longer repetition intervals. The changes to the repetition interval may be asymmetrical, such as decreasing additively and increasing multiplicatively.

Abstract: A food product slicing apparatus for slicing food products into slices is provided. A frame mounts a drive assembly which is configured to move the food products relative to the frame, a side strapping assembly which side straps a side of the food product, and a slicing blade configured to slice the food products into slices. The side strapping assembly is mounted to the frame proximate to the drive assembly. The side strapping assembly includes a releasable clamp which couples a blade of the side strapping assembly to the frame. The clamp can be released without the use of tools.

Abstract: A storage device may be coupled to a host device and the storage device may support a host performance booster (HPB) feature. A controller on the storage device may execute a background relocation operation. During the background relocation operation, the controller may identify a block to relocate data from. The controller may also determine that a relocation system threshold has not been reached. The controller may execute a source selection algorithm configured to minimize HPB entry inactivation resulting from data relocation. The source selection algorithm may include a criterion to enable the controller to select a source block for relocation.

Abstract: In a data storage device, a controller can optimize predictive loading using a hardware driven data path. In one or more examples, the controller may receive a first request for data from a host system. In response to detecting a pattern, and while transferring data, corresponding to the first request, the controller may load a first portion of data for a subsequent request for data, based on the pattern, from the device memory into a buffer. The controller may also initiate a transfer of a second portion of data for the subsequent request, to a latch in the device memory. In response to receiving the subsequent request, the controller may (i) transfer the first portion of data from the buffer, and (ii) transmit a read request to the device memory, for the second portion of data, thereby causing the device memory to transfer the second portion of data.

Abstract: A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.

Abstract: A semiconductor device and a formation method thereof are provided. The semiconductor device includes: a semiconductor substrate, where a plurality of columnar active areas are formed on the semiconductor substrate, the plurality of columnar active areas are spaced apart by a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction; a plurality of third trenches positioned in the semiconductor substrate at bottoms of the second trenches, where the third trenches are recessed to bottoms of the columnar active areas, and a bottom surface of a given one of the third trenches is higher than a bottom surface of the given first trench; and a plurality of metal silicide bit lines extending along the first direction in the semiconductor substrate positioned at the bottoms of the plurality of third trenches and the bottoms of the plurality of columnar active areas.

Abstract: A digital signal processor (DSP) with a global and local interconnection architecture includes a plurality of DSP hardware accelerator cores each including at least one DSP module for performing a DSP operation. The DSP further includes a global interconnect for data transfer between non-adjacent ones of the DSP hardware accelerator cores and between the DSP hardware accelerator cores and processing elements external to the DSP hardware accelerator cores. The DSP further includes a local stream interconnect associated with each of the DSP hardware accelerator cores for data transfer within each core and for data transfer between adjacent ones of the DSP hardware accelerator cores.

Abstract: Methods and apparatuses for assembling components are described. An apparatus in accordance with an aspect of the present disclosure comprises a first structure having a first tongue, a second tongue, and a third tongue, the second tongue being between the first tongue and the third tongue, a second structure having a first groove, a second groove, and a third groove, the second groove being between the first groove and the third groove, a first adhesive, coupled to the first tongue and the first groove and coupled to the third tongue and the third groove when the first structure is coupled to the second structure, and a second adhesive coupled to the second tongue and the second groove when the first structure is coupled to the second structure, wherein the first adhesive is injected into the first groove and the third groove and the second adhesive is injected into the second groove.

Abstract: A low-density, high-strength concrete composition that is lightweight and self-compacting or non-self-compacting, with a low weight-fraction of aggregate to total dry raw materials, and a highly-homogenous distribution of a non-absorptive and closed-cell lightweight aggregate such as glass microspheres or copolymer polymer beads or a combination thereof, and the steps of providing the composition or components. Lightweight concretes formed therefrom have low density, high strength-to-weight ratios, and high R-value. The concrete has strength similar to that ordinarily found in structural lightweight concrete but at a lower density, such as an oven-dried density as low as 40 lbs./cu.ft. Such strength-to-density ratios range approximately from above 30 cu.ft/sq.in. to above 110 cu.ft/sq.in., with a 28-day compressive strength ranging from about 3400 to 8000 psi.

Abstract: A signal control circuit includes: a generating circuit configured to accumulate execution times of an activation operation and output a block signal in response to an accumulated value being greater than or equal to a first preset value; and a logic circuit configured to receive an activation operation signal and the block signal, block outputting of the activation operation signal in response to receiving the block signal, and output the activation operation signal in response to not receiving the block signal.

Abstract: Provided is a softening agent for textiles characterized by containing a compound (A) and a crosslinking agent (B). The compound (A) is a non-silicone compound having a polyoxyalkylene chain in the molecule, and has a functional group (R1) capable of producing an ether, an ester, or a nitrogen-containing compound upon reacting with the crosslinking agent (B).

Abstract: The invention provides improved systems and methods for multiphoton microscopy including pixel clocking techniques for minimizing pixel integration time and providing consistent signal intensity with maximized imaging speeds. Various systems and method are described for optimizing laser repetition rate based on dye lifetime, combining polygonal mirror scanning and stage translation, using the laser pulse signal to time pixel collection, and minimizing laser pulses and dye usage based on signal to background ratios.

Abstract: Embodiments of the present disclosure provide a word line driver, a word line driver array, and a semiconductor structure, relating to the technical field of semiconductors. The word line driver includes: a zeroth P-channel metal oxide semiconductor (PMOS) transistor, a zeroth N-channel metal oxide semiconductor (NMOS) transistor, and a first NMOS transistor, the zeroth PMOS transistor being provided with a gate connected to a gate of the first NMOS transistor and configured to receive a first control signal, a source configured to receive a second control signal, and a drain connected to a drain of the first NMOS transistor, the zeroth NMOS transistor being provided with a gate configured to receive a second control complementary signal, and a drain of the zeroth NMOS transistor and the drain of the first NMOS transistor being configured to be connected to a word line.