Patents Assigned to TECHNOLOGIES INC.
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Patent number: 11552092Abstract: The present disclosure provides a semiconductor memory device and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor memory device includes a substrate, a source structure, a laminated structure, a floating body, a trench region, a drain structure and a gate structure. The source structure is formed on the substrate. The laminated structure includes a nitride layer and an oxide layer that are alternately laminated on the source structure. The floating body is formed in the oxide layer, and a through hole is formed in the floating body along a lamination direction of the laminated structure. The trench region is formed inside the floating body, a through hole is also formed in the trench region along the lamination direction, and the trench region is in contact with the source structure.Type: GrantFiled: January 12, 2022Date of Patent: January 10, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kui Zhang
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Patent number: 11551345Abstract: Systems and methods are provided to perform PdM surveys using data acquisition units which scan screen multiple locations where equipment or structures to be evaluated are present. Video data will be acquired and processed to measure translational and vibratory motion and additional data will be collected from other camera, sensors or via data links. The motion present in the equipment or structures under test and the supplemental data will be automatically evaluated to detect suspect equipment conditions and to minimize the amount of video data maintained on the data acquisition unit and transmitted back the central PdM server for review by a PdM analyst and long term archival.Type: GrantFiled: May 25, 2022Date of Patent: January 10, 2023Assignee: RDI TECHNOLOGIES, INC.Inventors: Kenneth Ralph Piety, Jeffrey R. Hay, Mark William Slemp
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Patent number: 11550756Abstract: A system and method for error-resilient data reduction, utilizing a phase detector, a data requestor, a multi-phase trainer, a reconstruction engine, a deconstruction engine, and one or more reference codebooks. A multi-phase trainer may be used to train the reconstruction and deconstruction engines on various phase sourceblocks in order recover quickly from corrupted data files that cause the phase alignment of the sourceblocks to become out of phase. A phase detector may determine when the sourceblocks get out of phase and when the return to in-phase by checking if a predetermined threshold probability of correct encoding is met. Data requestor may request for retransmission only the data that was received out of phase.Type: GrantFiled: April 19, 2021Date of Patent: January 10, 2023Assignee: ATOMBEAM TECHNOLOGIES INC.Inventors: Joshua Cooper, Aliasghar Riahi, Mojgan Haddad, Ryan Kourosh Riahi, Razmin Riahi, Charles Yeomans
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Patent number: 11552439Abstract: A laser projector steers a pulsed laser beam to form a pattern of stationary dots on an object, the pulsed laser beam having a periodicity determined based at least in part on a maximum allowable spacing of the dots and on a maximum angular velocity at which the beam can be steered, wherein a pulse width of the laser beam and a pulse peak power of the laser beam are based at least in part on the determined periodicity and on laser safety requirements.Type: GrantFiled: September 22, 2020Date of Patent: January 10, 2023Assignee: FARO TECHNOLOGIES, INC.Inventors: Arkady Savikovsky, Joel H. Stave
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Patent number: 11552675Abstract: Suppressing interference in a frequency hopping signal. The method includes receiving a frequency hopping signal for a signal of interest. The frequency hopping signal includes the signal of interest modulated using frequency hopping and wideband and narrowband interference. Prior to de-hopping the frequency hopping signal, one or more wideband interferences in the frequency hopping signal are identified. The one or more wideband interferences are suppressed to create a wideband interference suppressed signal. Subsequent to suppressing the one or more wideband interferences, the wideband interference suppressed signal is de-hopped to create a de-hopped signal. In the de-hopped signal, one or more narrowband interferences are identified. The one or more narrowband interferences are suppressed to create an interference suppressed signal. The interference suppressed signal is demodulated to create a demodulated signal.Type: GrantFiled: July 1, 2021Date of Patent: January 10, 2023Assignee: L3HARRIS TECHNOLOGIES, INC.Inventors: Lance R. Lindsay, L. Andrew Gibson, Christopher L. Brown, David G. Landon, Edwin R. Twitchell
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Patent number: 11553087Abstract: Implementations for providing communication services using a virtual environment are described. An audio communication session may be established between a first user device and a second user device. The second user device may answer the audio communication session using a virtual environment. The virtual environment may be updated to display virtual features associated with the communication session.Type: GrantFiled: September 29, 2020Date of Patent: January 10, 2023Assignee: AMAZON TECHNOLOGIES, INC.Inventors: William Arnold Cannady, Jeremy M. Puent, Kristopher Joseph Schultz
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Patent number: 11549330Abstract: A valve block may be assembled, in a controlled environment, a valve block to be modular and purpose built for a specific application. The specific application may be an operation to be performed at a well site. The modular purpose built valve block may be function tested, in the controlled environment. Additionally, the modular purpose built valve block may be pre-packaged, in the controlled environment, to have a digital system to operate and automate the modular purpose built valve block. Further, the modular pre-packaged purpose built valve block may be deployed to the well site, and the modular pre-packaged purpose built valve block may be fluidly coupled to a wellhead. The modular pre-packaged purpose built valve block may be operated to perform the operation at the well site.Type: GrantFiled: January 16, 2020Date of Patent: January 10, 2023Assignee: FMC TECHNOLOGIES, INC.Inventors: James Cook, Gareth Boyd, Julian Keihany, Thiago Machado
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Patent number: 11550560Abstract: Systems, methods, and related technologies for device software monitoring and device software updating are described. In certain aspects, a device is selected based on being a smart device and a software version of associated with the software of the device is determined. The device software may then be automatically updated if newer software is available.Type: GrantFiled: May 29, 2020Date of Patent: January 10, 2023Assignee: FORESCOUT TECHNOLOGIES, INC.Inventor: Siying Yang
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Patent number: 11548236Abstract: Techniques for providing universal interfaces between parts of a transport structure are disclosed. In one aspect of the disclosure, an apparatus for joining first and second parts of a transport structure includes an additively manufactured body having first and second surfaces. The first surface may connect to a first part such as, for example, a panel. The second surface may include a fitting for mating with a complementary fitting on a second part.Type: GrantFiled: March 2, 2021Date of Patent: January 10, 2023Assignee: DIVERGENT TECHNOLOGIES, INC.Inventor: Jon Paul Gunner
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Patent number: 11547968Abstract: The present invention provides: a gas separation method which is capable of desirably separating a slight amount of a component from a mixed gas under mild conditions such that the pressure difference between both sides of a gas separation membrane is 1 atmosphere or less; and a gas separation membrane which is suitable for use in this gas separation method. According to the present invention, in a gas separation method wherein a specific gas (A) in a mixed gas, which contains the specific gas (A) at a concentration of 1,000 ppm by mass or less, is selectively permeated with use of a gas separation membrane, an extremely thin gas separation membrane that has a film thickness of 1 ?m or less is used, so that the gas (A) is desirably separated under mild conditions such that the pressure difference between both sides of the gas separation membrane is 1 atmosphere or less.Type: GrantFiled: August 3, 2018Date of Patent: January 10, 2023Assignees: TOKYO OHKA KOGYO CO., LTD., NANOMEMBRANE TECHNOLOGIES, INC.Inventors: Takuya Noguchi, Takahiro Senzaki, Toshiyuki Ogata, Toyoki Kunitake, Shigenori Fujikawa, Miho Ariyoshi
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Patent number: 11548634Abstract: A modular aerial vehicle for inspection of enclosed and open space environments. The aerial vehicle is employed for inspection of various environments in remotely controlled and autonomous fashions. The aerial vehicle is capable of carrying different sensory modules depending on the specific application including surface inspection. Aerial vehicle may be connected to a tether cable for electrical power delivery and transmission of control commands. The aerial vehicle may utilize a landing structure which allows landing on any angled metallic or non-metallic surface.Type: GrantFiled: July 9, 2018Date of Patent: January 10, 2023Assignee: AVESTEC TECHNOLOGIES INC.Inventors: Mohammadreza Tavakolikhakaledi, Pouya Kamalinejad
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Patent number: 11547126Abstract: The present invention relates to methods and compositions for improving the quality of meat obtained from an animal. In one aspect, the method relates to feeding an animal a diet containing calcium nitrate. In one aspect, the method relates to improving the redness of the meat color.Type: GrantFiled: June 22, 2018Date of Patent: January 10, 2023Assignee: CAN TECHNOLOGIES, INC.Inventors: Alcina Ascensao, Brooke Humphrey, Ad Van Wesel
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Publication number: 20230005516Abstract: A signal generating circuit includes the following: a clock circuit, configured to receive an external clock signal to generate an internal clock signal; a controlling circuit, configured to generate a control signal according to the frequency of the external clock signal; and a generating circuit, connected with the clock circuit and the controlling circuit respectively, and configured to receive the internal clock signal, the control signal and a flag signal to generate a target signal. When the flag signal changes from a first level to a second level, the target signal is changed from a third level to a fourth level, and after the target signal maintains the fourth level for a target time length, the target signal is changed from the fourth level to the third level. The generating circuit is further configured to determine the target time length according to the internal clock signal and the control signal.Type: ApplicationFiled: February 17, 2022Publication date: January 5, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zequn HUANG
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Publication number: 20230005869Abstract: A method for forming a micro bump includes the following operations. A chip at least including a silicon substrate and a Through Silicon Via (TSV) penetrating through the silicon substrate is provided. A conductive layer having a first preset size in a first direction is formed in the TSV, the first direction being a thickness direction of the silicon substrate. A connecting layer having a second preset size in the first direction is formed on a surface of the conductive layer in the TSV, where a sum of the first preset size and the second preset size is equal to an initial size of the TSV in the first direction. The silicon substrate is processed to expose the connecting layer, for forming a micro bump corresponding to the TSV.Type: ApplicationFiled: February 12, 2022Publication date: January 5, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zengyan FAN
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Publication number: 20230005920Abstract: The semiconductor structure includes a first capacitive structure located on a substrate and first support columns. A plurality of first support columns are disposed on the substrate in parallel and spaced apart from each other, and are located in a same plane parallel to the substrate. The first capacitive structure includes a first lower electrode layer, a first dielectric layer and a first upper electrode layer. The semiconductor structure further includes a plurality of first segmentation trenches. The first segmentation trenches divide the first capacitive structure into a plurality of capacitors. A first insulation layer is disposed between the corresponding first lower electrode layers of the adjacent capacitors. The corresponding first upper electrode layers of the adjacent capacitors are electrically connected to each other.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES,INC.Inventors: Guangsu SHAO, Deyuan XIAO
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Publication number: 20230005919Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate, multiple active pillars located in the substrate, and multiple word lines. The multiple active pillars are arranged in an array in a first direction and a second direction. The first direction and the second direction are both directions parallel to a top surface of the substrate, and the first direction and the second direction intersect. The multiple word lines are spaced apart in the first direction. Each of the word lines extends in the second direction and continuously surrounds and covers a portion of a side wall of each of the multiple active pillars arranged in the second direction. Any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface of the substrate.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Deyuan XIAO, Yi JIANG, Guangsu SHAO, Xingsong SU, Yunsong QIU
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Publication number: 20230005559Abstract: A signal generation circuit includes: a clock module, configured to generate a clock signal based on a flag signal; a control module, configured to generate a control signal according to number of transitions of the clock signal within a fixed time; and a generation module, respectively connected to the clock module and the control module, and configured to receive the clock signal, the control signal, and the flag signal, and to generate a target signal. When the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level. After being maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level. The generation module is further configured to determine the target duration according to the clock signal and the control signal.Type: ApplicationFiled: September 30, 2021Publication date: January 5, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zequn HUANG
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Publication number: 20230004990Abstract: A system for preventing or inhibiting Payment Card fraud. When a Payment Card transaction is initiated, the card network conveys cardholder identifying information to the bank that issued the Payment Card. The issuing bank generate a random, one time data code (OTDC) upon receipt of cardholder identifying information. Alternatively, the cardholder may request an OTDC, by directly messaging the issuing bank or via an automated communication between the cardholder's mobile device and the issuing bank. The issuing bank then sends the cardholder an OTDC, preferably via an encrypted, secured transmission. The cardholder provides the OTDC to the merchant. The OTDC is part of the issuing bank's transaction approval criteria. The transaction should not be approved unless the merchant provides the OTDC to the issuing bank. The OTDC will only work for the transaction in question, and it will preferably expire shortly after its generation, if it remains unused.Type: ApplicationFiled: September 7, 2022Publication date: January 5, 2023Applicant: DUCKPOND TECHNOLOGIES, INC.Inventor: DARTANYON ANTWAUN WILLIAMS
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Publication number: 20230005810Abstract: A semiconductor structure includes: a substrate; a through silicon via structure that is located in the substrate; a first heat dissipation layer that is around a side wall of the through silicon via structure, and a material of which is a metal semiconductor compound; and a second heat dissipation layer that is around the side wall of the through silicon via structure and located between the first heat dissipation layer and the through silicon via structure, and a heat conductivity of which is greater than a heat conductivity of the first heat dissipation layer.Type: ApplicationFiled: December 8, 2021Publication date: January 5, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Luguang WANG, Xiaoling WANG
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Patent number: D974988Type: GrantFiled: June 3, 2021Date of Patent: January 10, 2023Assignee: MULLEN TECHNOLOGIES, INC.Inventor: Andreas Thurner