Abstract: An anti-fuse circuit includes the following: a first transistor, and at least one parasitic transistor and at least one parasitic triode that are connected to the first transistor. The at least one parasitic transistor and the at least one parasitic triode are connected to a first node.

Abstract: The present invention is directed to a dry suspension for reconstitution containing Tecovirimat (ST-246) powder and simethicone. The dry suspension is dispersed in water to provide an aqueous pharmaceutical suspension formulation for oral administration for treating orthopoxvirus infections and/or eczema vaccinatum. The suspension formulation exhibits excellent stability and good dissolution and has an improved taste and texture.

Abstract: A circuit simulation method includes the following: a key character string corresponding to at least one target power supply node is determined; a node identifier corresponding to the at least one target power supply node is searched out from a first netlist corresponding to the to-be-simulated circuit according to the key character string; and a power supply voltage file corresponding to the at least one target power supply node is generated according to the searched-out node identifier, and the to-be-simulated circuit is simulated according to the power supply voltage file. The circuit simulation method and the device provided by the embodiments of the present disclosure may rapidly generate the power supply voltage file corresponding to the target power supply node, which can not only effectively improve the circuit simulation efficiency, but also ensure the accuracy of a simulation result.

Abstract: A semiconductor structure includes a plurality memory group provided in rows, each of the memory groups includes a plurality of memories arranged at intervals along a row direction, and for two adjacent ones of the memory groups, the memories in one memory group and the memories in another memory group are staggered.

Abstract: A semiconductor structure includes a base, a dielectric layer, a gate structure, and a covering layer. The base includes discrete semiconductor pillars. The semiconductor pillars are disposed at the top of the base and extend in a vertical direction. The dielectric layer covers the sidewall of the semiconductor pillar. The gate structure is disposed in the middle area of the semiconductor pillar. The gate structure includes a gate-all-around structure, the gate-all-around surrounding the semiconductor pillar. A first part of the dielectric layer is disposed between the gate structures and the semiconductor pillars. The covering layer covers the top of the semiconductor pillar and part of the sidewall close to the top. The material of the covering layer includes a boron-containing compound.

Abstract: A gate valve device includes a cleaning component, a first lifting component, and a second lifting component. The cleaning component is arranged on the second lifting component. The first lifting component is configured to control whether an opening on a side of a vacuum chamber close to a swing gate valve is in a closed state. The second lifting component is configured to, in a case that the opening on the side of the vacuum chamber close to the swing gate valve is in the closed state, control the cleaning component to clean the swing gate valve.

Abstract: A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

Abstract: A semiconductor structure includes a substrate, and a plurality of first semiconductor columns, a storage structure, a plurality of transistors and a first protective layer located above the substrate. The plurality of first semiconductor columns are arranged in array in first and second directions. Each first semiconductor column includes a first part and a second part located on same. The second part includes a bottom portion, an intermediate portion and a top portion. The first direction and the second direction intersect with each other and are both parallel to top surface of the substrate. The storage structure surrounds sidewalls of the first parts. The first protective layer surrounds sidewalls of the top portions of the second parts. A channel structure of each transistor is located in the intermediate portion of the second part, and an extending direction of the channel structure is the same as that of the second part.

Abstract: A method for forming a semiconductor structure includes the following: providing a semiconductor substrate, in which stack structures and isolation structures alternately arranged along a first direction are formed on the semiconductor substrate; forming a support structure in the stack structures and the isolation structures; etching the stack structures and the isolation structures to form multiple zigzag first semiconductor pillars in an array arrangement along the first direction and a second direction, in which an interspace is formed between the zigzag first semiconductor pillars; each zigzag first semiconductor pillar comprises first convex structures and first concave structures alternately arranged along a third direction, and is supported by the support structure; the first direction, the second direction and the third direction are perpendicular to one another, and the second direction is perpendicular to a top surface of the semiconductor substrate; forming capacitor structures the interspace.

Abstract: Embodiments of the disclosure relate to the field of semiconductor technologies, and provide a layout and a wiring method, a comparison method, a fabrication method, a device, and a storage medium. The layout wiring method includes: obtaining names of all ports in a layout, each port has a first node and a second node; detecting whether the first node and the second node of each port are each connected to any other port through an actual connection layer, and if not, taking a port of which the first node and/or the second node are not connected to the actual connection layer as a port to be connected; and connecting at least two ports to be connected having the same name using a virtual connection layer.

Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming a semiconductor layer on the substrate; performing P-type doping on the semiconductor layer to transform the semiconductor layer into an initial mask layer; performing a first patterning treatment on the initial mask layer to form a mask layer having an opening; and performing a second patterning on the substrate by taking the mask layer as a mask and using an etching process. An etching rate of the substrate is greater than an etching rate of the mask layer during the etching process.

Abstract: A method for forming a semiconductor structure includes the following: a substrate is provided, the substrate including a first area and a second area arranged in sequence in a second direction and T-shaped active pillars located in the first area and the second area and arranged in an array in a first direction and a third direction, the first, second and third directions being perpendicular to one another, and the first and second directions being parallel to a surface of the substrate; T-shaped gate structures located on surfaces of the T-shaped active pillars and bit line structures extending in the third direction are formed in the first area, a plurality of T-shaped gate structures located in the first direction being interconnected; and capacitor structures extending in the second direction is formed in the second area, the bit line structures and the capacitor structures being connected to the T-shaped gate structures.

Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

Abstract: Disclosed are novel cellular populations generated by explosion of monocytic cells to conditioned media of regenerative cells. In one embodiment said regenerative cells are umbilical cord endothelial cells and said cells are pre-activated to possess enhance ability to reprogram said monocytic lineage cells. In one embodiment monocyte lineage cells are collected from leukopaks by plastic adherence and subsequently cultured in a manner to generate cells similar to M2 cells. In one embodiment said monocytic cells are cultured in a manner to generate myeloid derived suppressor cells. In one embodiment cells are generated to reducing inflammatory conditions. In another embodiment cells are generated for treatment of degenerative conditions. In another embodiment cells are generated for treatment of fibrosis.

Abstract: A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple first active pillars above the substrate, a memory structure, multiple transistors, and multiple second active pillars. The multiple first active pillars are arranged in an array along a first direction and a second direction. The substrate includes an isolation structure on which the first active pillars are located. The memory structure includes first electrode layers, a dielectric layer and a second electrode layer. The first electrode layer covers a sidewall of the first active pillar, the dielectric layer covers at least surfaces of the first electrode layers, the second electrode layer covers a surface of the dielectric layer. Each of the second active pillars is located above a corresponding one of the first active pillars; a channel structure of each transistor is located in the second active pillar.

Abstract: A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

Abstract: A method for detecting abnormity of a machine slot includes the following operations. A first failure rate is obtained. A second failure rate is obtained. A slot, of which the second failure rate is greater than or equal to the abnormity value, is marked as a target slot, and A slot, of which the second failure rate is smaller than the abnormity value, is marked as a control slot. An significance level of a difference between a failure rate of the target slot and a failure rate of the control slot in each day of the second time period is checked.

Abstract: A semiconductor package includes a first base plate, first semiconductor structure, second base plate and filling layer. The first base plate has a first surface including first and second signal transmission regions. The first semiconductor structure located on the first surface is electrically connected to the first signal transmission region. The second base plate located on the first base plate includes a base and a first interconnection surface. The first interconnection surface is away from the first surface. The first interconnection surface has first and second interconnection regions communicated with each other. The first interconnection region is electrically connected to the second signal transmission region. The filling layer seals the first semiconductor structure, second base plate and first surface. The first interconnection region is not sealed, and the second interconnection region is. There is a preset height between a top surface of the filling layer and the first interconnection region.

Abstract: A system and method for enforcing a patient's compliance with medicine dosage using an artificial intelligence engine to control a treatment apparatus. A method is disclosed for generating, by an artificial intelligence agent, a dosage compliance plan on a treatment apparatus. The method includes receiving one or more dosage compliance plans that, when applied to one or more users, encourage users to comply with medical prescriptions; receiving data associated with the user, wherein the data comprises at least one modified attribute of the user and at least one attribute of the medical prescription; receiving one or more constraints, wherein the one or more constraints comprises rules pertaining to dosage amounts associated with the one or more dosage compliance plans; and generating, via an artificial intelligence engine, an optimal dosage compliance plan for the user comprising the at least one modified attribute of the user associated with the at least one attribute of the medical prescription.

Abstract: A user device is caused to display a visual attribute representation for a plurality of visual attributes. Each visual attribute is based at least in part on an image and each visual attribute representation is selectable. A processor is caused to identify a plurality of items, each item is associated with a visual attribute matching at least one of the plurality of visual attributes. The items are classified a first set and a second set. The items in the first and second sets are mutually exclusive and simultaneously displayed. If the processor receives a single selection of a first visual attribute representation of a first visual attribute of the plurality of visual attributes, the first set consist of items associated with a visual attribute matching the first visual attribute and the second set comprise items associated with a visual attribute matching at least one of the plurality of visual attributes.