Patents Assigned to TECHNOLOGIES INC.
  • Publication number: 20230011347
    Abstract: A manufacturing method for a semiconductor structure includes: patterning and etching a semiconductor substrate to form a concave region; forming a first protective layer on a surface of the semiconductor substrate, the surface of the semiconductor substrate being a surface of a non-etched region except the concave region; forming an isolation structure in the concave region; and removing the first protective layer on the surface of the semiconductor substrate.
    Type: Application
    Filed: September 8, 2021
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chao WU
  • Publication number: 20230010014
    Abstract: A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided, and is etched to form first isolation trenches in a cell region and a second isolation trench in a peripheral region. A first isolation dielectric layer is filled in each of the first isolation trenches and an isolation structure is formed in the second isolation trench. A patterned mask layer is formed on surfaces of the cell region and the peripheral region. The substrate and the first isolation dielectric layer are etched based on the patterned mask layer to form the third isolation trenches extending along a second direction. The third and first isolation trenches isolate multiple active pillars. The active pillar includes a first connecting end, a second connecting end and a channel region.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Guangsu SHAO, Deyuan XIAO, YOUMING LIU, Yunsong QIU
  • Publication number: 20230012301
    Abstract: An Electrostatic Discharge (ESD) protection circuit includes a first discharge path and a second discharge path. The first discharge path is located between a first potential terminal and a second potential terminal. The second discharge path is located between the first potential terminal and the second potential terminal, and is connected to the first discharge path in parallel. The first discharge path and the second discharge path are used for discharging electrostatic charges. At least one of the first discharge path and the second discharge path includes a Silicon Controlled Rectifier (SCR).
    Type: Application
    Filed: April 1, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qian XU
  • Publication number: 20230010338
    Abstract: An input sampling method includes the following operations. A first pulse signal and a second pulse signal are received. Logical operation is performed on the first pulse signal and the second pulse signal to determine a to-be-sampled signal. The to-be-sampled signal is obtained by shielding an invalid part of the second pulse signal according to a logical operation result. Sampling process is performed on the to-be-sampled signal to obtain a target sampled signal.
    Type: Application
    Filed: February 16, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zequn HUANG
  • Publication number: 20230008633
    Abstract: A semiconductor structure includes a Through Silicon Via (TSV) and a protective ring disposed outside the TSV; the protective ring includes at least two protective layers arranged in parallel and surrounding the TSV; each of the protective layers includes a first protective structure and second protective structures disposed surrounding the first protective structure; the first protective structure is a polygonal structure; a number of sides of the polygonal structure is greater than or equal to 4; and the second protective structures are disposed on an inner side and an outer side of each corner area of the polygonal structure.
    Type: Application
    Filed: June 19, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: TZUNG-HAN LEE, CHIH-CHENG LIU
  • Publication number: 20230011549
    Abstract: In some examples, an organizer may include a plurality of inserts. At least one insert of the plurality of inserts may include at least a front panel and an opposite back panel that form the at least one insert, and at least one instrument component disposed hi the at least one insert. The organizer may further include a binding mechanism that attaches the plurality of inserts.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 12, 2023
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventors: Shaouhan HU, Daniela Loraing, Olga Schikurski, Sascha Lege, Stephan Buckenmaier
  • Publication number: 20230012066
    Abstract: A comparator includes a first-stage circuit, a second-stage circuit, a first switching circuit and a second switching circuit. The first-stage circuit includes a first input circuit and a second input circuit. The first switching circuit is configured to control the conduction of the first input circuit, and the second switching circuit is configured to control the conduction of the second input circuit. The first input circuit is configured to generate a first differential signal in a sampling phase when being switched on. The second input circuit is configured to generate a second differential signal in a sampling phase when being switched on. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.
    Type: Application
    Filed: April 6, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yinchuan GU
  • Publication number: 20230008991
    Abstract: A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.
    Type: Application
    Filed: April 20, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Tianchen LU
  • Publication number: 20230008265
    Abstract: A semiconductor testing structure forming method includes: a semiconductor substrate is provided, and the semiconductor substrate includes a plurality of active areas arranged separately; a first conductive wire is formed at a preset distance from the plurality of active areas in the semiconductor substrate, and the first conductive wire is connected with a substrate of a respective active device formed in each of the plurality of active areas; a plurality of first contact holes is formed on the first conductive wire; and a first metal layer is formed on top of each of the plurality of first contact holes to obtain the semiconductor testing structure, where the first metal layer is electrically connected with a first common pad and the first common pad is configured to perform an electric performance test on the semiconductor testing structure.
    Type: Application
    Filed: November 7, 2021
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiangyu WANG, Haibo CHEN
  • Publication number: 20230011186
    Abstract: A memory includes a plurality of semiconductor structures stacked onto one another. Each of the plurality of semiconductor structures include: a first base including a peripheral circuit structure; a first integrated circuit layer disposed on the first base and electrically connected to the peripheral circuit structure; and a second base disposed on the first integrated circuit layer. A first dielectric layer is disposed between the first integrated circuit layer and the second base. The second base includes a storage circuit structure. Each of the first base and the second base includes a semiconductor layer.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengmeng YANG, JIE BAI, Deyuan XIAO
  • Publication number: 20230011840
    Abstract: A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.
    Type: Application
    Filed: February 13, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Wei CHANG
  • Publication number: 20230010642
    Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, at least a gate structure, a first dielectric layer covering a surface of the substrate and the gate structure being formed on the substrate, and a first dielectric layer on a side surface of the gate structure serving as a first sidewall; forming a sacrificial sidewall on a side surface of the first sidewall; removing the sacrificial sidewall after a first doped region and a second doped region are respectively formed in the substrate on both sides of the sacrificial sidewall; forming a second sidewall on a side surface of the first sidewall.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yi TANG
  • Publication number: 20230011367
    Abstract: A high reliability drug infusion device, includes: a drug storage unit including a drug outlet; a screw connected to a piston and a driving wheel provided with wheel teeth, respectively, the driving wheel drives the screw to move by rotation, pushing the piston forward; at least one driving unit cooperating with the driving wheel, the driving unit includes at least one driving portion a power unit and a reset unit connected to the driving unit, and the reset unit includes an elastic reset component and a linear-actuated reset component, and the elastic reset component alone applies a force to or together with the linear-actuated reset component to control the reset movement of the driving unit. The high reliability drug infusion can be used for improving the reliability and increasing the user's flexibility in choosing the infusion method.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 12, 2023
    Applicant: MEDTRUM TECHNOLOGIES INC.
    Inventor: Cuijun YANG
  • Publication number: 20230012005
    Abstract: A method for manufacturing a semiconductor structure includes: providing a base having first contact layers and a second contact layer; forming an initial electrical connection layer; forming a lower mask layer including a first and a second pattern regions, and on an upper surface of the base, orthographic projections of two first contact layers fall within an orthographic projection of one first pattern region, and an orthographic projection of one second contact layer falls within an orthographic projection of one second pattern region; patterning the first pattern region to form two first sub-pattern regions discrete from each other; and etching the initial electrical connection layer to form first electrical connection layers and a second electrical connection layer discrete from each other, in which the first electrical connection layers correspond to the first sub-pattern regions, and the second electrical connection layer corresponds to the second pattern region.
    Type: Application
    Filed: December 8, 2021
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: You LV
  • Publication number: 20230011266
    Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided, and the substrate includes an active surface and a back surface opposite to the active surface. An etching stop layer is formed on the back surface of the substrate. The substrate is fixed onto a first temporary carrier to make the etching stop layer be located between the substrate and the first temporary carrier. The substrate is etched until reaching the etching stop layer to form a via structure penetrating through the substrate.
    Type: Application
    Filed: February 17, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Ling-Yi CHUANG
  • Publication number: 20230009877
    Abstract: A semiconductor memory includes a main memory area and a tag memory area. A plurality of memory groups are set in the main memory area and a plurality of flag bits are set in the tag memory area. Each of the plurality of memory groups has a corresponding relationship with one of the plurality of flag bit. The flag bit is at least configured to indicate whether at least one memory cell in the memory group has a specific state. The specific state includes an occupied state.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Huan LU
  • Publication number: 20230011180
    Abstract: Provide is a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes the following operations. A substrate is provided. Multiple silicon pillars are formed in the substrate, and extend along a first direction. In the first direction, each of the silicon pillars includes a first portion and a second portion. An insulating layer is formed in the second portion of the silicon pillar. A conductive layer is formed in the first portion of the silicon pillar. A capacitor layer is formed on surfaces of the insulating layer and the conductive layer of the silicon pillar.
    Type: Application
    Filed: September 7, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengmeng YANG, Yi Tang
  • Publication number: 20230009103
    Abstract: A method for forming a semiconductor device includes the following: after sacrificial side walls are formed on the side walls of conductive connection structures, forming an outer side wall material layer on the surfaces of the sacrificial side walls; perforating the outer side wall material layer to form pinholes in the outer side wall material layer which expose the surfaces of the sacrificial side walls; removing the sacrificial side walls through the pinholes to form air gaps; and forming a cover layer for sealing the pinholes.
    Type: Application
    Filed: February 12, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: DAEJOONG WON
  • Publication number: 20230008364
    Abstract: A method for identifying a latch-up structure includes the following: in a chip layout, a first N-type heavily doped region connected to a first input/output pad and located in a P-type substrate is found; a first P-type heavily doped region located in an N-well and a second P-type heavily doped region located in the P-type substrate, both of which are adjacent to the first N-type heavily doped region, are found; a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the N-well is found, wherein the N-well is located on the P-type substrate; and an area formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well and the P-type substrate is identified as the latch-up structure.
    Type: Application
    Filed: March 30, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qian XU
  • Publication number: 20230008332
    Abstract: A parsing method includes the following: during parsing target bank, performing a row hammer operation on a logical row in target bank to determine a physical position relationship of the logical row; repeatedly performing the operation of performing the row hammer operation on the logical row in target bank to determine the physical position relationship of the logical row until all logical rows have been parsed; and determining a mapping relationship used for recording physical position relationships of multiple logical rows according to a linked list; where performing the row hammer operation on the logical row in target bank includes: acquiring a to-be-parsed logical row in target bank including multiple logical rows; performing the row hammer operation on the to-be-parsed logical row until at least one flipped logical row is obtained; and writing the at least one flipped logical row into the linked list.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiaolei LI, Baolei HAN