Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 11442852
    Abstract: Aspects of a storage device including a master chip controller and a slave chip processor and memory including a plurality of memory locations are provided which allow for simplified processing of descriptors associated with host commands in the slave chip based on an adaptive context metadata message from the master chip. When the controller receives a host command, the controller in the master chip provides to the processor in the slave chip a descriptor associated with a host command, an instruction to store the descriptor in the one of the memory locations, and the adaptive context metadata message mapping a type of the descriptor to the one of the memory locations. The processor may then process the descriptor stored in the one of the memory locations based on the message, for example, by refraining from identifying certain information indicated in the descriptor. Reduced latency in command execution may thereby result.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: September 13, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Todd Lindberg, Robert Ellis, Kevin O'Toole, Vivek Shivhare
  • Patent number: 11445636
    Abstract: A vapor chamber that includes a housing including a first sheet and a second sheet opposing each other and joined together at outer edges of the first sheet and the second sheet and defining a hollow vapor flow pass therein; a working fluid in the housing; a first wick in contact with the vapor flow pass; and a second wick between the first wick and an inner wall surface of at least one of the first sheet and the second sheet. The first wick defines a first liquid flow pass, the second wick defines a second liquid flow pass, and a first average diameter of the first liquid flow pass is smaller than or equal to 75% of a second average diameter of the second liquid flow pass.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 13, 2022
    Assignees: MURATA MANUFACTURING CO., LTD., KELVIN THERMAL TECHNOLOGIES, INC.
    Inventors: Takuo Wakaoka, Tatsuhiro Numoto, Keijiro Kojima, Ryan J. Lewis
  • Patent number: 11440679
    Abstract: A mechanically secure docking platform for unmanned VTOL aircraft (“drone”) or other automated vehicle, acting as an automated battery recharging system for drones or a battery quick change system for drones. The system also is capable of enabling an automated data logistics system for drones, an autonomous guidance system for landing and docking for drones, and/or an autonomous guidance system for undocking and takeoff for drones.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: September 13, 2022
    Assignee: COWDEN TECHNOLOGIES, INC.
    Inventor: Jason Patrick Cowden
  • Patent number: 11442440
    Abstract: The present disclosure provides a method and an apparatus of handling a control wafer, a method of testing by using a control wafer, a computer-readable storage medium and an electronic device, and relates to the technical field of semiconductor equipment. The method of handling a control wafer includes: setting different identification numbers for multiple reaction chambers; determining slot numbers of control wafers according to the identification numbers of the reaction chambers; and distributing the control wafers according to the slot numbers of the control wafers and the identification numbers of the reaction chambers.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: September 13, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: San-Chen Chen
  • Patent number: 11444086
    Abstract: The present invention relates to a capacitor and its formation method and to a DRAM cell. In various embodiments, a substrate is provided such that an electrical contact portion is formed thereon. A dielectric layer is formed on a surface of the substrate, including alternately stacked supporting layers and sacrificial layers. At least two capacitor holes penetrating the sacrificial layers and the supporting layers can formed to expose the same electrical contact portion. A lower electrode layer covering the inner surface of the capacitor holes can be formed. The lower electrode layer is connected to the electrical contact portion. The sacrificial layers are then removed and a capacitor dielectric layer and an upper electrode layer are formed successively on the inner and outer surfaces of the lower electrode layer and on the surface of the supporting layers. This can increase capacitance value per unit area of the capacitor.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: September 13, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chi-Wei Dai
  • Patent number: 11442163
    Abstract: A real-time aircraft bird congestion indicator system for measuring congestion in an airspace between aircraft and birds uses one or more radars to continuously survey an airspace around an airport or aerodrome and continuously generate aircraft tracks and bird tracks in the airspace. A congestion processor connected to the radar(s) receives the aircraft and bird tracks and processes them to periodically generate a congestion indicator that measures the congestion in the airspace. A display processor connected to the congestion processor receives the congestion indicator which is updated periodically by the congestion processor and displays the congestion indicator to a user, generates an alert if the congestion indicator falls outside set operating limits, and/or sends the congestion indicator or alert to another system.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: September 13, 2022
    Assignee: ACCIPITER RADAR TECHNOLOGIES INC.
    Inventors: Timothy J. Nohara, Peter T. Weber, Graeme S. Jones, Ilia Choly, Robert Fraser
  • Publication number: 20220284011
    Abstract: A system for implementing distributed blockchain transactions that includes: a first participant blockchain comprising a first node; second participant blockchain comprising a second node; and a coordinator blockchain comprising a coordinator node is disclosed. The distributed transaction involves a first transaction on the first participant blockchain, and a second transaction on the N second participant blockchain.
    Type: Application
    Filed: August 5, 2020
    Publication date: September 8, 2022
    Applicant: ZEU TECHNOLOGIES, INC.
    Inventors: Yuming QIAN, Francois DUMAS, Patricia POPERT-FORTIER, Jean-Philippe BEAUDET
  • Publication number: 20220285363
    Abstract: The present application provides a memory and a memory fabricating method. The memory includes a substrate, on which is disposed a separation layer, in which are arranged plural bitlines spaced apart from one another, the plural bitlines are arranged along a first direction, and each bitline is S-shaped. The method of fabricating the memory comprises the following steps: providing a substrate; forming on the substrate plural bitline grooves; forming in each bitline groove a first separation layer; forming bitlines on the first separation layer; forming a second separation layer on the bitlines; removing the substrate between adjacent separation walls, the separation wall including the first separation layer, the bitlines, and the second separation layer; and forming a third separation layer in a space between the adjacent separation walls, the third separation layer, the second separation layer, and the first separation layer together forming a separation layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: September 8, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengzhu QIAO, Tao CHEN
  • Publication number: 20220285481
    Abstract: A method for forming a semiconductor structure includes: forming a base including a substrate, capacitor contacts in the substrate, a laminated structure disposed on a surface of the substrate capacitor holes penetrating through the laminated structure and exposing the respective capacitor contacts, the laminated structure including a plurality of support layers and at least one sacrificial layer which are alternately stacked along a direction perpendicular to the substrate, and a lower electrode layer covering inner walls of the capacitor holes; forming a protective layer covering a surface of the lower electrode layer; etching part of the support layer to expose the sacrificial layer; and removing all the sacrificial layers and all the protective layer to expose the lower electrode layer.
    Type: Application
    Filed: August 22, 2021
    Publication date: September 8, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kangshu ZHAN, Qiang WAN, Penghui XU, Tao LIU, Sen LI, Jun XIA
  • Publication number: 20220285204
    Abstract: A method for preparing a semiconductor device includes: providing a semiconductor substrate, in which a trench is formed on the semiconductor substrate, a filling layer is formed in the trench, and a void is formed in the filling layer; removing a portion of the filling layer to expose the void; forming a plug, in which the plug is configured to plug the void and extends into the void by at least a preset distance; and removing a portion of the filling layer and remaining the plug with at least a preset height until the filling layer reaches a preset thickness to form a contact hole.
    Type: Application
    Filed: August 8, 2021
    Publication date: September 8, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jingwen LU, HAI-HAN HUNG, MENG-CHENG CHEN
  • Publication number: 20220285352
    Abstract: A memory includes a substrate. An isolation layer is disposed on the substrate. The plurality of active regions arranged in an array are disposed in the isolation layer. A plurality of word lines are formed in the plurality of active regions and the isolation layer. Each word line includes gates disposed in the active regions and word line structures disposed in the isolation layer. The each word line is constituted by successive connection of the plurality of gates and the plurality of word line structures arranged at intervals. The plurality of gates included in the each word line are disposed in two correspondingly adjacent columns of active regions, and any two adjacent gates in the each word line are disposed in two correspondingly adjacent rows of active regions.
    Type: Application
    Filed: September 8, 2021
    Publication date: September 8, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Tao CHEN
  • Publication number: 20220285187
    Abstract: A treatment method for an OOC action during a semiconductor production process includes: multiple Out Of Control Action Plan IDs (OCAPID) respectively corresponding to multiple semiconductor production process steps and multiple identified contents in one-to-one correspondence with the multiple OCAPIDs are established, and an OOC action checklist including multiple OOC action check items according to the identified contents is established; it is determined whether the OOC action occurs to a wafer subjected to the current semiconductor production process step, and if the OCC action occurs to the wafer, the current OCAPID corresponding to the current semiconductor production process step is automatically obtained, and the wafer is inspected according to the current identified content corresponding to the current OCAPID.
    Type: Application
    Filed: August 30, 2021
    Publication date: September 8, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jun WANG
  • Patent number: 11436552
    Abstract: A method may include the following steps: determining, based on timing measurements between a first digital radio communication device (DRCD) node and at least a second DRCD node, a distance between the first DRCD disposed on a tanker and the second DRCD disposed about a loading/unloading facility; and facilitating, in response to determining a position based on the timing measurements, fluid payload loading/unloading of the tanker at the loading/unloading facility.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 6, 2022
    Assignee: FMC TECHNOLOGIES, INC.
    Inventors: Frederick G. Weiser, James M. Pettinato, Jr., Iulian Constantinescu
  • Patent number: 11433728
    Abstract: An active control system for a mass traveling along a guideway and method for active control of a mass traveling along a guideway. The active control system includes at least one displacement sensor and at least one motion sensor. Signals from the at least one displacement sensor and the least one motion sensor are processed to adjust a displacement of a reference location on the mass from a fixed reference.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 6, 2022
    Assignee: HYPERLOOP TECHNOLOGIES, INC.
    Inventor: Irfan-ur-rab Usman
  • Patent number: 11437698
    Abstract: A magnet-less multi-port ring combiner comprises a set of ports extending from the circumference of the magnet-less multi-port ring combiner. The set of ports are positioned at ¼ increments around the circumference of the magnet-less multi-port ring combiner. The set of ports comprise a first input port configured to receive a first input signal and a second input port configured to receive a second input signal, wherein the first input signal is 180° out-of-phase with the second input signal. The N-way magnet-less multi-port combiner comprises more than four ports.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 6, 2022
    Assignee: L3HARRIS TECHNOLOGIES, INC.
    Inventors: Kyle David Holzer, Jeffrey Walling
  • Patent number: 11437996
    Abstract: The present disclosure relates to a dynamic control conversion circuit, which includes: a dynamic control unit configured to generate a dynamic control signal according to a received input signal; a first semiconductor switch, a control terminal of the first semiconductor switch is connected with a first signal output terminal of the dynamic control unit, and a first terminal of the first semiconductor switch is connected with a first voltage terminal; a second semiconductor switch, a control terminal of the second semiconductor switch is connected with a second signal output terminal of the dynamic control unit; and a circuit output unit having a first control terminal connected with a second terminal of the first semiconductor switch and a first terminal of the second semiconductor switch, and a second control terminal connected with a second terminal of the second semiconductor switch and a third signal output terminal of the dynamic control unit.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: September 6, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: WeiBing Shang, Sungsoo Chi, Ying Wang
  • Patent number: 11434068
    Abstract: A filter pad with a dry loft between approximately 0.15 and 0.5 inches includes at least a first fiber web comprising a plurality of oleophilic fibers, wherein the oleophilic fibers: have a linear density between approximately 2 and 9 denier; have a length between approximately 1 and 4 inches; and have been uploaded with flame resistant particles.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: September 6, 2022
    Assignee: RESTAURANT TECHNOLOGIES, INC.
    Inventors: Glenn David Alexander, Joseph Anthony Salpietra, Jordan Salpietra
  • Patent number: 11437949
    Abstract: A method may include obtaining a normal set point of a solar panel and a wind velocity measurement corresponding to wind that affects the solar panel. The method may include determining an allowable range of tilt angles according to a first lookup table that describes a relationship between the wind velocity measurement and the allowable range of tilt angles. The method may include identifying whether the normal set point of the solar panel is outside of the allowable range of tilt angles, and responsive to identifying that the normal set point of the solar panel is outside of the allowable range of tilt angles, determining a temporary stow set point. The method may include rotating the solar panel to the temporary stow set point.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: September 6, 2022
    Assignee: ARRAY TECHNOLOGIES, INC.
    Inventors: Lucas Creasy, Todd DarVel Andersen, Jon Andrew Sharp, James John Stoshak, Sanket Shah, James Fusaro
  • Patent number: D962958
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: September 6, 2022
    Assignee: ARISTOCRAT TECHNOLOGIES, INC.
    Inventors: Patrick Collins, Victor Blanco, Michelle Cupersmith
  • Patent number: D963692
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: September 13, 2022
    Assignee: PALANTIR TECHNOLOGIES, INC.
    Inventors: Ashley Einspahr, Andrew Elder, Brandon McCain, Claire Adrien