Abstract: A data storage device, such as a solid state drives (SSD), includes command completion interrupt coalescing. A controller of the data storage device includes one or more completion queues, each including interrupt coalescing protection logic. The interrupt coalescing protection logic detects that a head pointer or a tail pointer in a completion queue has not changed for a predetermined period of time. When the head and tail pointers have not changed for the predetermined period of time, the controller posts an interrupt to a host device.

Abstract: Magnetic recording media including a soft magnetic underlayer (SUL) formed over an oxidized pre-seed layer. In some examples, the pre-seed layer is oxidized to reduce an amount of intermixing between the pre-seed layer and the SUL. The reduction in intermixing via oxidation can lead to improved recording performance of the recording media that are deposited on the SUL. In particular, media overwrite, signal-to-noise ratio (SNR), linear recording density, and areal recording density or areal density capacity (ADC) can be improved. In one aspect, a deposition apparatus may be modified to inject oxygen during pre-seed layer deposition to oxidize the pre-seed layer.

Abstract: According to one method, the method occurs at a test system. The method includes receiving test configuration information for testing a NFV infrastructure; configuring, using the test configuration information, at least one virtual resource tester (VRT) for testing one or more virtual resources of the NFV infrastructure; configuring at least one VNF tester for testing at least one VNF associated with the NFV infrastructure, wherein the at least one VNF tester is deployed in a same environment as the at least one VNF and wherein the at least one VNF tester is instructed to perform behaviors that attempt to impact performance of the at least one VNF; testing the NFV infrastructure using the at least one VRT and the at least one VNF tester; and monitoring performance of the NFV infrastructure during testing using information obtained from at least one test related entity.

Abstract: Optical products and methods of making them are disclosed, the optical products comprising a polymeric substrate and a composite coating. The composite coating, in turn, comprises: a first layer comprising a polyionic binder, and a second layer comprising insoluble particles that absorb electromagnetic energy and insoluble particles that absorb relatively little visible light. Each of the first layer and the second layer includes a binding group component which together form a complimentary binding group pair.

Abstract: A cleaning method includes: providing a wafer, the wafer having a wafer edge; and controlling the wafer in a rotation phase to rotate the wafer, and providing a cleaning solution for the wafer edge in the rotation phase. The rotation phase includes a first rotation phase and/or a second rotation phase. A rotation speed of the wafer increases from a first speed to a second speed during the first rotation phase, and the rotation speed of the wafer decreases from the second speed to the first speed during the second rotation phase. The second speed is greater than the first speed.

Abstract: A semiconductor device includes a stack of semiconductor dies, stacked in a stepped offset configuration, where the dies have different storage capacities and different sizes. Using dies of different sizes allows dies to be added to the stack without adding to the footprint of the semiconductor device. Using dies of different storage capacity also allows semiconductor devices to be tailored to specific storage capacity needs.

Abstract: A simulation method and device, a power wire topology network, and a test circuit involve: a power wire topology network is generated according to a power wire layout, the power wire topology network including a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element, the parasitic element being located between the two power child nodes; a minimum voltage of the power input node of each circuit nodule in a circuit corresponding to the power wire topology network is determined, the power input node being one of the power child nodes in each circuit module; and a time sequence simulation is performed according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of an integrated circuit.

Abstract: The present invention is a process, a method, and system for recovery and concentration of dissolved ammonium bicarbonate from a wastewater containing ammonia (NH3) using gas separation, condensation, and crystallization, each at controlled operating temperatures.

Abstract: Disclosed are methods of ameliorating, inhibition, and/or reversing diabetes utilizing immune cells that have been reprogrammed ex vivo by contact with regenerative cells. In one embodiment said reprogrammed immune cells comprise peripheral blood mononuclear cells obtained from the patient in need of treatment wherein said cells are endowed with properties of immune modulation, and/or suppression of inflammation, and/or restoration of insulin sensitivity, and/or pancreatic regeneration. In one embodiment regenerative cells used for reprogramming are mesenchymal stem cells. In one particular embodiment said cells are umbilical cord derived mesenchymal stem cells. Culture of peripheral blood mononuclear cells together with said regenerative cells is performed in the presence of interleukin-2 and/or an mTOR inhibitor. In one embodiment said mTOR inhibitor comprises rapamycin and/or a derivative thereof.

Abstract: The invention discloses a micro-analyte detection device, which comprises a bottom case, the bottom board of the bottom case is provided with a mounting hole; a sensor structure, the sensor structure includes a sensor and a sensor base, and the sensor includes a signal output end and a detection end, and a transmitter, the transmitter includes a transmitter housing and an electronic device, the electronic device is provided with an electrical connection area, when the transmitter is installed in the working position, the electrical connection area is electrically connected with the signal output end. This device effectively reduces the overall thickness of the analyte detection device and enhances the user experience.

Abstract: A storage system includes: a memory, configured to write or read a plurality of pieces of data during a read-write operation, the plurality of pieces of data being divided into M bytes, and each byte having N pieces of data; and an encoding circuit, configured to in the encoding stage, generate X first check codes based on the two or more pieces of data in each byte, generate Y second check codes based on all data of two or more bytes of the M bytes in the encoding stage, and generate a third check code based on the plurality of pieces of data, the X first check codes and the Y second check codes. The first check codes, the second check codes and the third check code are used to determine an error state of the plurality of pieces of data.

Abstract: A protection circuit can be applied in a chip, and include: a first protection unit and a first element to be protected, wherein the first protection unit is configured to receive a first input signal and a control signal, and is configured to output a first output signal, the first element to be protected includes a first P-type transistor, and a gate of the P-type transistor is configured to receive the first output signal. When the chip enters a burn-in test, the first output signal is a high-level signal.

Abstract: Methods, apparatuses and methods of manufacture are described for a MEMS mirror array with reduced crosstalk. The MEMS mirror array has a plurality of reflective surfaces wherein each reflective surface has a resonant frequency, and further wherein adjacent reflective surfaces do not have the same resonant frequency.

Abstract: A preparation method for the capacitor structure includes: forming a dielectric layer on a first electrode, wherein, the dielectric layer includes a first amorphous layer and a high dielectric constant layer which are stacked, the first amorphous layer maintaining an amorphous structure after annealing, and the high dielectric constant layer being formed by crystallizing an initial dielectric constant layer after annealing; and forming a second electrode on the dielectric layer. Since the first amorphous layer remains an amorphous structure after annealing, electron transport can be suppressed, thereby reducing the leakage current of the capacitor structure.

Abstract: A manufacturing method of a semiconductor structure includes: a substrate is provided; and an intermediate layer is formed on the substrate, an I-shaped member and a wall-shaped member are formed in the intermediate layer, a top surface of the wall-shaped member is not lower than a top surface of the I-shaped member, and a bottom surface of the wall-shaped member is not higher than a bottom surface of the I-shaped member.

Abstract: A manufacturing method of the semiconductor structure includes: providing a semiconductor substrate, and forming a gate region and a source-drain region on the semiconductor substrate; forming an insulating dielectric layer which covers both of the gate region and the source-drain region; patterning the insulating dielectric layer on the source-drain region to form a first contact hole exposing the source-drain region; forming a metal silicide at the bottom of the first contact hole; patterning the insulating dielectric layer on the gate region to form a second contact hole of which an orthographic projection on the semiconductor substrate is located on the gate region; and forming a filling layer in the first contact hole and the second contact hole.

Abstract: Embodiments of the present application provide a self-refresh frequency detection method, including: writing data to at least one wordline in a memory; performing a self-refresh operation on the memory; setting, after a clock enable signal changes to a low level, a duration of the low level; performing a reading operation on the memory at a positive trip point of the clock enable signal; acquiring a plurality of reading results corresponding to a plurality of durations of the low level; and obtaining a self-refresh frequency of the memory according to the plurality of durations of the low level and the plurality of reading results. The embodiments of the present application are conducive to improving the simplicity of self-refresh frequency detection.

Abstract: A conformal cooling assembly for multiple-die electronic assemblies, such as printed circuit boards, integrated circuits, etc., which addresses and solves a multitude of challenges and problems associated with using liquid-cooled cold plates and dielectric immersion cooling to manage the heat produced by a multiplicity of dies. The conformal cooling assembly comprises a conformal cooling module comprising inlet and outlet passageways and a plenum configured to permit a cooling fluid to pass therethrough, thereby facilitating direct fluid contact with heat-generating components affixed to the substrate of the electronic assembly. The conformal cooling assembly also includes a fastener for attaching the conformal cooling module to the substrate; and a fluid-barrier disposed between the substrate and the plenum. The fluid-barrier is adapted to minimize, inhibit or prevent the cooling fluid from penetrating and being absorbed by the substrate.

Abstract: The present application relates to a semiconductor structure, a method for forming the semiconductor structure, and a fuse array. The semiconductor structure includes at least two first through holes located above a substrate, a first conductive layer located above and electrically connected with the first through holes, at least two second through holes located above the first conductive layer, and a second conductive layer located above the second through holes and electrically connected with the first conductive layer through the second through holes, wherein projections of the first through holes and the second conductive layer on the substrate are non-overlapping. The semiconductor structure requires relatively low fusing energy.

Abstract: A storage system comprises a non-volatile memory configured to store boot code and a control circuit connected to the non-volatile memory. In response to a first request from a host to transmit the boot code, the storage system commences transmission of the boot code to the host at a first transmission speed. Before successfully completing the transmission of the boot code to the host at the first transmission speed, it is determined the boot code transmission has failed. Therefore, the host will issue a second request for the boot code. In response to the second request for the boot code, and recognizing that this is a fallback condition because the previous transmission of the boot code failed, the storage apparatus re-transmits the boot code to the host at a lower transmission speed than the first transmission speed.