Abstract: A method for fusing and filling a semiconductor structure includes: a semiconductor structure body is provided, a plurality of fuse array groups is formed in the semiconductor structure body; at least one of interconnection structures of the fuse array groups is fused to form at least one notch in the semiconductor structure body; a shielding layer is formed on the semiconductor structure body, at least one through hole exposing the at least one notch is formed in the shielding layer; and a sealing material layer is formed in the notch.
Abstract: A method for forming an ultra-shallow junction includes the following operations: providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, providing a dopant and implanting the dopant into the epitaxial layer and a part of the semiconductor substrate, and removing the epitaxial layer, to form the ultra-shallow junction.
Abstract: A method for forming a semiconductor structure can include the following steps. A substrate and an insulating layer that are stacked are provided, the substrate having a plurality of storage node contact structures spaced apart from each other. A grid-like upper electrode layer is formed on a surface of the insulating layer, where the upper electrode layer has a plurality of meshes penetrating the upper electrode layer, and an orthographic projection of each of the meshes on the insulating layer and an orthographic projection of a storage node contact structure on the insulating layer have an overlapping area. A dielectric layer is formed on a side wall of each mesh. The insulating layer exposed from the mesh is removed to expose the storage node contact structure. A lower electrode layer is formed inside each mesh.
Abstract: In some embodiments, the instant invention provides for specifically programming a computer machine to perform at lease: receiving, from a trader, a passive indication of interest (IOI) for a financial instrument, where the passive IOI is a bid or an offer and a resting liquidity; classifying the trader as at least: a trading type that is subject to a decline ratio calculation for crossing the passive IOIs, where the decline ratio calculation identifies how many eligible aggressive IOIs have been previously declined by the trader out of a total number of all eligible aggressive IOIs that were offered to such trader; receiving, from another trader, another TOT that is an aggressive IOI where the aggressive IOI is available to be immediately crossed at the price; and determining, in real-time, an allocation of the aggressive IOI to the trader submitted the passive TOT based on the decline ratio of the trader.
Type:
Application
Filed:
April 25, 2022
Publication date:
August 11, 2022
Applicant:
GREEN KEY TECHNOLOGIES, INC.
Inventors:
Anthony Tassone, Matt Martorello, Justin Martorello
Abstract: An enhanced vision system includes a first optic subsystem and a transparent photodetector subsystem disposed within a common housing. The first optic subsystem may include passive devices such as simple or compound lenses, active devices such as low-light enhancing image intensifiers, or a combination of passive and active devices. The transparent photodetector subsystem receives the visible image exiting the first optic subsystem and converts a portion of the electromagnetic energy in the visible image to a signal communicated to image analysis circuitry. On a real-time or near real-time basis, the image analysis circuitry detects and identifies structures, objects, and/or individuals in the visible image. The image analysis circuitry provides an output that includes information regarding the structure, objects, and individuals to the system user contemporaneous with the system user viewing the visible image.
Type:
Grant
Filed:
May 4, 2017
Date of Patent:
August 9, 2022
Assignee:
L3 TECHNOLOGIES, INC.
Inventors:
Jon Burnsed, Stephen Styonavich, Michael Iosue
Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A first block of data is channel encoded into first channel data based on a channel code constraint, and the first channel data is error correction encoded to generate first redundancy bits. A second block of data is channel encoded into second channel data based on the channel code constraint and the first redundancy bits, and the first channel data and the second channel data are error correction encode to generate second redundancy bits. A third block of data is channel encoded into third channel data based on the channel code constraint and the second redundancy bits. The first, second and third channel data and the first and second redundancy bits are stored in the NVSM.
Type:
Grant
Filed:
February 19, 2021
Date of Patent:
August 9, 2022
Assignee:
WESTERN DIGITAL TECHNOLOGIES, INC.
Inventors:
Iouri Oboukhov, Richard L. Galbraith, Niranjay Ravindran
Abstract: The present disclosure generally related to a two dimensional magnetic recording (TDMR) read head having a magnetic tunnel junction (MTJ). Both the upper reader and the lower reader have a dual free layer (DFL) MTJ structure between two shields. A synthetic antiferromagnetic (SAF) soft bias structure bounds the MTJ, and a rear hard bias (RHB) structure is disposed behind the MTJ. The DFL MTJ decreases the distance between the upper and lower reader and hence, improves the area density capacity (ADC). Additionally, the SAF soft bias structures and the rear head bias structure cause the dual free layer MTJ to have a scissor state magnetic moment at the media facing surface (MFS).
Abstract: A hard disk drive comprises a carriage assembly that comprises a carriage-arm tip with a swaging hole centered about a swaging axis. A first head-gimbal assembly comprises a tension baseplate on a first side of the carriage-arm tip with a tension swage boss located within the swaging hole. A second head-gimbal assembly comprises a compression baseplate on a second side of the carriage-arm tip with a compression swage boss located with the swaging hole. The tension swage boss comprises an uppercut that extends radially outward, away from the swaging axis, from a first backbore diameter to a second backbore diameter and a tension-boss undercut that extends radially outward, away from the swaging axis, from a tension-boss outer diameter to a first undercut diameter. The compression swage boss comprises a compression-boss undercut that extends radially outward, away from the swaging axis, from a compression-boss outer diameter to a second undercut diameter.
Abstract: Logs representative of interactions by users or services with interfaces, such as clickstream logs, are generated by combining logs associated with cached data with logs associated with data generated in response to a request. When a first response to a request is generated and a portion of the response data is cached, a first log representative of interactions with the cached data is stored in association with a log identifier. When a second request is received at a subsequent time and the cached data is used to generate a second response, a second log representative of interactions with the response data will include the log identifier for the first log. In response to the log identifier, the first log is accessed and combined with the second log to form a third log representative of interactions with both the cached data and response data for the second response.
Abstract: The present disclosure provides methods, uses and compositions and kits for use in inducing an antibody immune response in a human subject. The methods and uses involve administering parenterally a low dose volume of a composition comprising an antigen comprising a B-cell epitope, an amphipathic compound, and a hydrophobic carrier, wherein the low dose volume of the composition is less than 100 ?l and induces an antibody immune response to the B-cell epitope in the human subject.
Type:
Grant
Filed:
September 27, 2016
Date of Patent:
August 9, 2022
Assignee:
IMMUNOVACCINE TECHNOLOGIES INC.
Inventors:
Marc Mansour, Frederic Ors, Marianne Stanford, Leeladhar Sammatur, Rajkannan Rajagopalan, Lisa Diana MacDonald
Abstract: An image sensor includes a photodiode array and a color filter array optically aligned with the photodiode array. The photodiode array includes a plurality of photodiodes disposed within respective portions of a semiconductor material. The color filter array includes a plurality of color filters arranged to form a plurality of tiled minimal repeating units. Each minimal repeating unit includes at least a first color filter with a red spectral photoresponse, a second color filter with a yellow spectral photoresponse, and a third color filter with a panchromatic spectral photoresponse.
Type:
Grant
Filed:
August 3, 2020
Date of Patent:
August 9, 2022
Assignee:
OMNIVISION TECHNOLOGIES, INC.
Inventors:
Chen-Wei Lu, Yin Qian, Eiichi Funatsu, Jin Li
Abstract: A user undertakes an event, such as adding, removing, or otherwise interacting with an item stowed at a fixture. Using successive samples of weight data that occur during an event, a plurality of vectors are generated that are indicative of a weight change and a location associated with the fixture. The vectors are processed to determine where within the fixture the event took place. Hypotheses are generated that describe predicted interactions involving predicted locations that correspond to those indicated by the vectors. The hypotheses are ranked and then one is selected as a solution. The predicted values associated with the selected hypothesis are then used to generate interaction data that indicates one or more types of item and quantities of the items that were added, removed, or otherwise handled by the user.
Type:
Grant
Filed:
June 28, 2016
Date of Patent:
August 9, 2022
Assignee:
AMAZON TECHNOLOGIES, INC.
Inventors:
Nikhil Chacko, Robert Crandall, Paul Eugene Munger, Liefeng Bo, Gerard Guy Medioni
Abstract: A thermally-assisted magnetic recording head includes a medium facing surface, a main pole, a waveguide, and a plasmon generator. A second metal layer of the plasmon generator includes a second front end facing the medium facing surface. A third metal layer of the plasmon generator includes a narrow portion located on the second metal layer. The narrow portion includes a front end face located in the medium facing surface and configured to generate near-field light from a surface plasmon, and a rear end opposite the front end face. The rear end is located farther from the medium facing surface than is the second front end.
Abstract: The present disclosure discloses a method for forming a semiconductor structure. The method for forming a semiconductor structure includes: providing a base; forming a dielectric layer on the base; forming one or more openings in the dielectric layer; and forming an anti-reflective coating in the one or more openings. When forming the anti-reflective coating, alternating current is applied around the base.
Abstract: A method for testing wireless communications devices includes controlling a wireless environment simulator for creating a simulated wireless environment around a device under test (DUT). The DUT includes a wireless communications system. The method further includes stimulating the DUT as specified by a test case and recording, using a test monitor, one or more wireless signals transmitted between the DUT and the wireless environment simulator in response to stimulating the DUT. The method further includes generating a test result for the DUT based on comparing performance data from the wireless signals with expected performance specifications for the test case.
Abstract: A head-mounted wearable device (HMWD) with a form factor of eyeglasses incorporates hinges between a front frame and temples. The hinges provide a fully enclosed passage for a flexible printed circuit (FPC). The FPC allows electrical connectivity between devices in the front frame and in the temple. The hinge includes a cam device that provides a biasing force that allows the temples to remain in one of four configurations: closed, transit, neutral, and maximum neutral. When in the transit configuration the biasing force provided by the cam device tends to move the temples towards the closed configuration. When in the maximum neutral configuration the biasing force provided by the cam device tends to move the temples towards the neutral configuration. During use, this biasing of the temples provides a gentle clamping force that assists in maintaining the HMWD on the user's head.
Type:
Grant
Filed:
March 5, 2018
Date of Patent:
August 9, 2022
Assignee:
AMAZON TECHNOLOGIES, INC.
Inventors:
Chun Sik Jeong, Jung Sik Yang, Niranjan Madan Mohan Bhatia, Yuna Hu, Jianchun Dong, Zhen Xu, Han Zhang
Abstract: A method and system for reducing power consumed in processing units when processing units are used to calculate computationally expensive linear functions on a sequence of correlated data. Processing of a new data sample may be performed to consume less power by using results obtained from the processing a previous reference data sample.
Abstract: A system may include a data delivery pipeline communicatively coupled to one or more microservices that receive a dataset transmitted through the data delivery pipeline. The system may also include a first microservice that receives a first dataset corresponding to operation technology (OT) data or information technology (IT) data and determines a second dataset based on the first dataset. The system may also include a second microservice that receives the second dataset from the first microservice via the data delivery pipeline, determines an action to perform in an industrial automation component of an industrial automation system based on an analysis of the second dataset, and transmits the action to the industrial automation component via the data delivery pipeline.
Abstract: A method and system to surreptitiously inject data into a data stream over a communication channel including an error correction encoder circuit to apply an error correction scheme to a data stream to create an unfaulted data, a binary to bit value positioner that converts bits in confidential data to corresponding position value of bits in a packet, and a data stream encoder that flips a bit in the unfaulted data based on the binary to bit value positioner to create a bit-faulted data.
Abstract: The embodiments of the present disclosure provide a method for manufacturing a capacitor array structure, a capacitor array structure and a semiconductor memory device. The method for manufacturing a capacitor array structure includes: providing a substrate; forming a capacitor structure on the substrate; wherein the capacitor structure includes a bottom electrode layer formed on the substrate, a capacitor dielectric layer formed on a surface of the bottom electrode layer, and a top electrode layer formed on a surface of the capacitor dielectric layer; and there is gaps formed by the top electrode layer; forming a filling layer to fill the gaps; forming a covering layer to cover the filling layer and the top electrode layer; wherein, the covering layer is combined with the filling layer to define a top electrode conductive layer.