Abstract: Devices and techniques are generally described for object matching in image data. In various examples, first image data and second image data may be received. A first feature map representing the first image data and a second feature map representing the second image data may be generated. The first feature map and second feature map may be combined and a first and second segmentation mask may be generated using the combined feature map. The first segmentation mask may be used to filter the first feature map to generate a filtered representation. The second segmentation mask may be used to filter the second feature map to generate a filtered representation. A determination may be made that a first object depicted in the first image data corresponds to a second object depicted in the second image data using the filtered representations.
Type:
Grant
Filed:
March 30, 2022
Date of Patent:
March 18, 2025
Assignee:
AMAZON TECHNOLOGIES, INC.
Inventors:
Ioana-Sabina Stoian, Alin-Ionut Popa, Ionut Catalin Sandu, Daniel Voinea
Abstract: User enrollment to a biometric identification system begins on selected general input devices (GID) such as smartphones. The user may enter identification data (e.g. name) and use a red-green-blue (RGB) camera of the GID to acquire a first image (e.g. hand). The first image is processed using both a first model to determine a first representation and a second model to determine a second representation. Upon presentation of a hand at a biometric input device, a second image is acquired using a first modality and a third image is acquired using a second modality. The second image is processed using the first model to determine a third representation. The third image is processed using the second model to determine a fourth representation. Given a match between both the first and third representations, as well as the second and fourth representations, enrollment is completed by storing the third and fourth representations.
Type:
Grant
Filed:
March 25, 2024
Date of Patent:
March 18, 2025
Assignee:
AMAZON TECHNOLOGIES, INC.
Inventors:
Quanfu Fan, Hongcheng Wang, Carlos D. Castillo, Manoj Aggarwal, Gerard Guy Medioni
Abstract: Systems and methods of support structures in powder-bed fusion (PBF) are provided. Support structures can be formed of bound powder, which can be, for example, compacted powder, compacted and sintered powder, powder with a binding agent applied, etc. Support structures can be formed of non-powder support material, such as a foam. Support structures can be formed to include resonant structures that can be removed by applying a resonance frequency. Support structures can be formed to include structures configured to melt when electrical current is applied for easy removal.
Type:
Grant
Filed:
April 28, 2017
Date of Patent:
March 18, 2025
Assignee:
DIVERGENT TECHNOLOGIES, INC.
Inventors:
Eahab Nagi El Naga, John Russell Bucknell, Chor Yen Yap, Broc William TenHouten, Antonio Bernerd Martinez
Abstract: A semiconductor structure and a forming method thereof are provided. The method for forming a semiconductor structure includes providing a base including a semiconductor substrate and a well region located on a surface of the semiconductor substrate, in which the well region includes a plurality of active pillar columns arranged at intervals along a first direction, and each of the active pillar columns includes a plurality of active pillars arranged at intervals along a second direction, in which the first direction is perpendicular to the second direction; forming a plurality of bit line trenches by etching at least the well region and a partial thickness of the semiconductor substrate at bottoms of the active pillars; and forming buried bit lines in the bit line trenches.
Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method of manufacturing a semiconductor structure, a semiconductor structure and a memory. The method of manufacturing a semiconductor structure includes: forming a first semiconductor layer on a substrate, the first semiconductor layer including a first trench region and a to-be-doped region on two opposite sides of the first trench region; forming a word line, the word line surrounding a sidewall surface of a part of the first semiconductor layer in the first trench region, and at least a part of a projection of a part of the first semiconductor layer in the to-be-doped region on a surface of the substrate coinciding with a projection of the word line on the surface of the substrate; forming a doping body portion, the doping body portion including first dopant ions.
Abstract: Embodiments of the present disclosure disclose a semiconductor base plate and a semiconductor device. An array region includes a primary memory cell. A peripheral region includes an antifuse memory cell. The antifuse memory cell and the primary memory cell are formed by a same process.
Abstract: A test circuit includes first integration circuit configured to receive first test signal and integrate first test signal to output first integrated signal; second integration circuit configured to receive second test signal and integrate second test signal to output second integrated signal, where first test signal and second test signal are signals inverted with respect to each other, value of first integrated signal is product of duty cycle of first test signal and a voltage amplitude of power supply, and value of second integrated signal is product of duty cycle of second test signal and voltage amplitude of power supply; and comparison circuit connected to first and second integration circuits. The comparison circuit is configured to output high-level signal in response to first integrated signal being greater than second integrated signal, and output low-level signal in response to second integrated signal being greater than first integrated signal.
Abstract: A method for selectively processing a packet flow using a flow inspection engine is disclosed. The method includes receiving, by at least one hardware data plane processor component in a network packet broker, a plurality of packets associated with a packet flow, and forwarding, by the at least one hardware data plane processor component to at least one flow inspection engine, a copy of at least a portion of one or more of the initial packets of the packet flow.
Type:
Grant
Filed:
March 15, 2022
Date of Patent:
March 18, 2025
Assignee:
KEYSIGHT TECHNOLOGIES, INC.
Inventors:
Jonathan Lee Harrod, Shardendu Pandey, Jonathan Glenn Stroud, Stefan Jan Johansson
Abstract: The present disclosure provides a method of forming a photoresist pattern and a projection exposure apparatus. The forming method includes: providing a photoresist layer, and disposing the photoresist layer under a projection objective, wherein a light refracting plate is located between the photoresist layer and the projection objective; and performing an exposure processing on the photoresist layer through the projection objective and the light refracting plate, and forming an exposure image in the photoresist layer, wherein the light refracting plate is configured to reduce a wavelength of optical waves entering the photoresist layer.
Abstract: The present disclosure provides a semiconductor structure, a method of reading data from the semiconductor structure, and a method of writing data into the semiconductor structure. The semiconductor structure includes: a memory matrix, including a plurality of magnetic storage domains arranged in a staggered manner and including a first end, a second end, and an intermediate portion; and a reading and writing circuit, connected to the intermediate portion of the memory matrix and configured to write data into the magnetic storage domains and read data from the magnetic storage domains.
Abstract: An optical device includes an underlying device configured output light to an optical output to output an image of objects in an environment to a user. The light is output in a first spectrum. A stacked device is configured to be coupled in an overlapping fashion to an optical output of the underlying device. The stacked device is transparent, according to a first transmission efficiency, to light in the first spectrum. The stacked device includes a plurality of electro-optical circuits including: a plurality of light emitters configured to output light, and a plurality of detectors configured to detect light in the first spectrum from the underlying device that can be used to detect the objects in the image. The light emitters are configured to output light dependent on light detected by the detectors and additional information about characteristics of the objects in the environment.
Abstract: Process for treating sludge includes a first segment in which a batch of sludge and lime are mixed with the addition of supplement heat to achieve an elevated processing temperature and a second segment in which the mixer is maintained at a lower temperature to dry the interior of the mixing device after processing the batch.
Abstract: A method for processing text data includes analyzing the text data to identify a plurality of keywords. The method also includes determining whether each of the plurality of keywords already exists in one or more databases. When a keyword in the plurality of keywords is not found in the one or more databases, the method includes tagging the keyword with a plurality of characters for storage. The plurality of characters includes at least a first character to indicate a start of the tagging, a second character to indicate a corresponding database for storing the keyword, and a third character to indicate an end of the tagging. The method also includes storing the tagged keyword in the corresponding database.
Type:
Grant
Filed:
August 31, 2023
Date of Patent:
March 18, 2025
Assignee:
ZINATT TECHNOLOGIES, INC.
Inventors:
Gabriel Enrique Reina, David Hirschfeld
Abstract: Aspects of a storage device are provided that perform partial decryption of host encrypted data and encryption of host provided data using received or generated keys for data targeted for compute services. The storage device may include a non-volatile memory and a controller. The controller may receive encrypted data, receive a key associated with a portion of the encrypted data, and decrypt the portion of the encrypted data based on the key without decrypting a remainder of the encrypted data. The controller may also receive data, receive or generate a key associated with a portion of the data, encrypt the portion of the data based on the key without encrypting a remainder of the data based on the key, and store the encrypted portion of the data in the non-volatile memory for subsequent decryption. As a result, a balance between encrypted data storage and decrypted data security may be achieved.
Abstract: Systems and methods for embodiments of artificial intelligence systems for identity management are disclosed. Embodiments of the identity management systems disclosed herein may support the correlation of identities from authoritative source systems and accounts from non-authoritative source systems using artificial intelligence techniques.
Type:
Grant
Filed:
March 8, 2024
Date of Patent:
March 18, 2025
Assignee:
SAILPOINT TECHNOLOGIES, INC.
Inventors:
Mohamed M. Badawy, Rajat Kabra, Jostine Fei Ho
Abstract: A scoring system and method identifies personal attacks in a piece of audio content and generates a civility score for the piece of audio content that can differentiate between personal attacks and vernacular/casual banter. The piece of audio content may be a podcast.
Type:
Grant
Filed:
December 21, 2023
Date of Patent:
March 18, 2025
Assignee:
SEEKR TECHNOLOGIES INC.
Inventors:
Robin J. Clark, Ali Taleb Zadeh Kasgari, Stefanos Poulis
Abstract: A memory structure of an integrated circuit includes a plurality of memory arrays arranged in parallel along the first direction and extending along the second direction, a sensitivity amplifier array extending along the second direction is arranged between every two memory arrays, and the sensitivity amplifier array includes an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array, the odd-numbered sensitivity amplifier array is connected to an odd-numbered global signal line, and the even-numbered sensitivity amplifier array is connected to the even-numbered global signal line; a first sensitivity amplifier array is arranged between the memory arrays at the edge, and the first sensitivity amplifier array is connected to both the odd-numbered global signal line and the even-numbered global signal line. The present disclosure can improve reliability, yield and test success rate of the memory products.
Abstract: Systems and method for dynamically managing add-on orders within a delivery service application. For example, a computer-implemented method includes obtaining data indicative of a primary order request. The method includes selecting, ranking, and displaying menu items for add-on orders associated with a primary order. The method includes obtaining user data provided by a user through a user interface associated with a delivery service application. The method includes determining, in response to obtaining the user data, that the primary order request is eligible for an add-on order. The method includes determining merchants for the add-on order. The selected merchants can be determined from a plurality of candidate merchants based at least in part on analysis of merchant-specific data relative to the user data indicative of the primary order request. The method includes updating the user interface to display data associated with the one or more selected merchants for the add-on order.
Type:
Grant
Filed:
April 29, 2022
Date of Patent:
March 18, 2025
Assignee:
UBER TECHNOLOGIES, INC.
Inventors:
Robert Louis Cornacchia, Emre Demiralp, Cinar Kilcioglu, Kevin A. Rowe, Zhengyun Sun, Vishnu Sundaresan, Ameya Tayade, Justin Wie
Abstract: An anti-fuse unit structure includes a substrate, an anti-fuse device, and a select transistor. The anti-fuse device is formed in the substrate and comprises a first gate structure, a first source doped region, and a first drain doped region, wherein the first gate structure is electrically connected to the first drain doped region. The select transistor is formed in the substrate and matched with the anti-fuse device, and comprises a second gate structure, a second source doped region and a second drain doped region, wherein the second drain doped region is electrically connected to the first source doped region.