Abstract: An ECL to CMOS converter having a diferential ECL clock input and an ECL data input is provided. A reference voltage is generated by averaging the level shifted differential ECL clock signals using a voltage divider. This reference voltage and the level shifted ECL data input are compared by a CMOS comparator to provide a CMOS data output. The level shifters, comparators, and the voltage divider are integrated in a standard VLSI CMOS process that enables the resultant integrated circuit to operate from a single supply voltage.

Abstract: A pattern of conductor runs is formed on a sheet of dielectric material using a carrier foil having a coating material adhered to one main surface thereof. The coating material contains particles of metal. The carrier foil is placed with its coated surface in contact with the sheet. The coating material is detached from the carrier foil over selected areas of its coated surface, and the detached coating material is adhered to the sheet.

Abstract: A signal processing system for a spectrum analyzer presents a three-dimensional display of a signal in the form of a display of an independent variable, such as frequency, versus a selected property of the signal, such as power, where the selected property is represented as a distribution of values for each independent variable interval in the form of intensity variation on the display. The independent variable is divided into m slots, and the selected property is sampled k times for each slot. A histogram for each slot is built up in a buffer representing the number of samples occurring at each of n power levels. The histogram is transferred to a display memory column by column for each slot, and after all the slots have been processed the display memory is read out onto a display device, such as a CRT, in a raster scan format with the intensity of each pixel element being a function of the number or samples at that power level within that frequency interval.

Abstract: A phase change ink carrier composition is combined with a compatible colorant to form a phase change ink composition of this invention. A thin film of substantially uniform thickness of that phase change ink carrier composition, and the ink produced therefrom, has a high degree of lightness and chroma. The thin films of a substantially uniform thickness of the ink composition are also rectilinearly light transmissive. The carrier composition is preferably a fatty amide-containing compound.

Abstract: A combined optical power meter and receiver is provided in which the optical power meter retains high sensitivity and the optical receiver retains high bandwidth. A single photodiode provides current for both the optical power meter and the optical receiver. A first operational amplifier is configured as an integrating transimpedance amplifier having a current input which is referenced to a reference voltage and receives current from one port of the photodiode. A second operational amplifier is configured as a transimpedance amplifier having a current input which is referenced to ground and receives current from the other port of the photodiode. In this manner, a bias voltage is developed across the photodiode to decrease the capacitance and increase the operational speed of the receiver. A second material photodiode is provided which is shielded from the input light source is coupled to the current input of the first transimpedance amplifier.

Abstract: A recursive noise reduction filter for video components reduces the noise bandwidth of a signal without degrading the signal spectrum. Demodulated chrominance or peak detected chrominance from a video signal output by a video system in reponse to a video test signal is input to the recursive noise reduction filter which acts as a comb filter to suppress noise significantly at frequencies other than harmonics of the horizontal line rate. The signal is scaled by a first attenuator having a scaling factor of (1-a), where (a) is less than one, and input to a summing circuit. Also input to the summing circuit is a delayed signal from a prior horizontal line scaled by the scaling factor (a). The output of the summing circuit is a filtered output signal. The signal is sampled only during horizontal lines that have the video test signal and is stored for subsequent accumulation with other horizontal lines also having the video test signal.

Abstract: An f.sub.T doubler amplifier having a Darlington type common base stage is provided wherein the fast current contributions from the f.sub.T doubler are passed through the slow path of the Darlington common base stage, and the slow current contributions from the f.sub.T doubler are passed through the fast path of the Darlington common base in order that the delay of each current contribution is more closely matched. In this way, the distributed nature of the amplifier and resultant phase distortion are minimized and transient response is improved.

Abstract: A method for producing a light-transmissive phase change ink printed substrate is described which comprises providing a substrate, and then printing on at least one surface of the substrate a predetermined pattern of a light-transmissive phase change ink which initially transmits light in a non-rectilinear path. The pattern of solidified phase change ink is then reoriented to form an ink layer of substantially uniform thickness. This ink layer will, in turn, produce an image which then will transmit light in a substantially rectilinear path.In one aspect of the invention, the substrate is light transmissive, and the reoriented printed substrate exhibits a high degree of lightness and chroma, and transmits light in a substantially rectilinear path. In this way, the reoriented printed substrate can be used in a projection device to project an image containing clear, saturated colors.

Abstract: An apparatus for storing multi-bit pixel data comprises a random access memory, for storing a plurality of pixels at each addressable memory location, the memory having one write enable and one data input for each bit of each pixel at a currently addressed memory location. Means are provided to couple each line of a data bus to the write enable inputs associated with corresponding bits of each addressed pixel and to place a common bit, in a selected state, on every data input assosciated with a corresponding bit of each currently addressed pixel, thereby permitting a processor to rewrite the addressed pixels with a selected pixel value, provided the write enables of each pixel are activated by an appropriate bit on the associated data bus line, and thereby permitting a processor to write pixel data to the memory using only one bit per pixel on the data bus.

Abstract: A digital trigger for a digitizing instrument having multiple analog-to-digital converters employed in interleaved fashion and in which the clock phase and period of a trigger point can be accurately determined. The digital trigger includes a digital comparator for comparing the output signals of each analog-to-digital converter to a trigger threshold level to generate a trigger signal at the output of the comparator if a trigger point occurs on the output signal. The outputs of the collective digital comparators are routed to decoding logic which generates a digital signal that indicates the phase of the clock period in which the trigger point occurred. The outputs of collective digital comparators are also logically ORed together for detecting if a trigger point occurred during a clock period.

Abstract: A circuit for subtracting wide band signals without requiring an amplifier having good common mode rejection converts each wide band signal into opposing currents. A switching network applies the desired current for each wide band signal to a summing node. The combined current at the summing node is input to a drive amplifier to produce an output signal that is the desired combination of the wide band signals.

Abstract: A timing measurement system for displaying data path and clock jitter moves an internal copy of the data clock with respect to the incoming data and clock to acquire sets of samples for each data path and the clock at sequential delay intervals. A reference time is established by examining the clock sets and determining skew extremes defined by the times when the values within a set are no longer all at one state and when the values are all at the other state. The skew extremes are averaged to establish the reference time. Likewise each data path set is examined to determine skew extremes, and the skew extremes are displayed as shaded areas with respect to the reference time for each data path. Also the clock signal is converted to a stable clock signal that is also compared in a like manner to the input clock to establish skew extremes that are displayed about the reference time as clock jitter.

Abstract: A "diagramming debugger" creates a graphical representation of the sequence of messages sent during operation of an object-oriented program. When one object transmits a message to another object, the diagramming debugger displays representations of the transmitting and receiving objects on a computer screen, each representation comprising a box with labels identifying the represented object. The box representing a sending object includes therewithin a symbol (comprising, for example, one or more characters) identifying the method that sent the message, while the box representing the receiving object includes therewithin a symbol identifying the method invoked by the message. The message is represented by an arrow pointing from the symbol identifying the sending method to the symbol identifying the invoked method.

Abstract: A sample-and-hold circuit for sampling a time-varying signal comprises a main sample-and-hold subcircuit extending between input and output terminals and an auxiliary sample-and-hold subcircuit extending between the input terminal and a portion of the main subcircuit. Each sample-and-hold subcircuit comprises an input buffer amplifier, a diode-bridge switch responsive to a control signal and coupled to the input buffer amplifier, a charge-holding capacitor coupled to the switch, and an output buffer amplifier coupled to the capacitor. The output of the auxiliary output amplifier is further coupled to the main switch and the output of the main output amplifier is coupled to the output terminal. A generator generates the control signal for controlling the switches such that the same part of the time-varying signal passing through the main and auxiliary subcircuits is sampled.

Abstract: An electron beam addressed liquid crystal light modulator or "valve" (10) includes a liquid crystasl cell (40) having a target surface (45) which a writing electron beam (60a) and an erasing electron beam (60b) address to provide a display image. The writing electron beam and the erasing electron beam sequentially strike preselected locations on the target surface to cause an emission of secondary electrons and, thereby, develop an electrostatic potential at such preselected locations. A secondary electron collector electrode (66) positioned over and above the target surface collects in a uniform manner the secondary electrons emitted by all regions of the target surface. A collector electrode controller circuit (81) sequentially applied first and second potential differences between the target surface and the collector electrode in synchronism with the striking of the preselected locations by the respective writing and erasing beams.

Abstract: A differential amplifier in the form of a Gilbert gain cell is controlled by a pair of input currents applied to a pair of differentially coupled transistor pairs. A digital signal is generated and input into a CMOS digital-to-analog converter (DAC). The DAC outputs a pair of currents on conductors which are maintained at virtual ground by the use of a current mirror and an operational amplifier. The control signals applied to the differentially coupled transistor pairs are generated as base currents of transistors conducting the DAC output currents.

Abstract: A device for generating a digitizing pulse for sampling an analog video signal includes a phaes-locked-loop (PLL) circuit and a phase offset circuit. The PLL circuit generates a correction pulse required to bring an output signal of digitizing pulses in phase with a reference horizontal sync signal. The phase offset circuit includes a digital memory which stores a digital number representative of a fraction of a pixel pulse that is desired as phase offset of the digitizing pulse. This fraction is converted into an offset current pulse having a duration equal to the duration of a pixel pulse and an amplitude that is the fraction of a maximum amplitude. The offset current is added to the PLL correction current for generating an output signal of digitizing pulses having the desired phase offset relative to the pixel pulses.

Abstract: The trajectory across a surface of an intended target point of a moving beam directed toward the surface is digitized by finding a particular point along each of a plurality of parallel axes of the surface for which a two-dimensional convolution integral of two functions is a maximum. A first of the two functions is the instantaneous intensity distribution of the beam on the surface with respect to the instantaneous position of the target point on the surface. The second function is the average beam intensity distribution on the surface produced as the beam moves across the surface during a finite period. A digital data sequence is generated in which each element thereof represents the position on the surface of a separate one of the particular points determined in this fashion, and this sequence represents the trajectory of the target point of the beam on the surface.

Abstract: Operation of a microcomputer-based instrument is controlled by software including a control interface system, a command execution system, and a steady state system. The steady state system includes a group of subsystems operating as concurrent tasks, each carrying out various instrument operations. The control interface system includes a set of subsystems, each responsive to configuration control input signals from a separate control signal source, and each converting configuration control signals into "configuration commands". Each command identifies a particular procedure for configuring the operating state of one or more instrument hardware or software steady state subsystems of the instrument. Each command is stored in memory in one of several queues (one for each control interface subsystem) until the procedure it invokes is carried out.

Abstract: A thermally stabilized optical preamplifier includes a first transimpedance amplifier which receives a photosignal current from a photodiode. The gate of a GaAs device is the input to the first transimpedance amplifier, and the drain is coupled to a source of constant current. Also coupled to the drain of the GaAs device is a common base stage, and the gain of the first transimpedance amplifier is set by a resistor coupled between the input of the first transimpedance amplifier and the output of the common base stage. A current setting resistor coupled to the output of the first transimpedance amplifier converts output voltage to current, which is summed with a compensating current in a second transimpedance amplifier. The compensating current consists of a variable current generator and a thermal current generator which compensate for the current produced by the absolute value and thermal characteristics of the gate to source voltage of the input GaAs device.