Abstract: A probe holder for a signal acquisition probe has a cradle receiving the signal acquisition probe and a pedestal adapted for receiving substrates of various thicknesses. The pedestal has a base member and an upright member with the upright member coupled to the cradle. The base member has at least a first lateral slot formed therein having a plurality of clearances for receiving substrates of varying thicknesses.

Abstract: A mixed signal measurement instrument provides for the display of both analog and logic signal waveforms using a “no dead time” architecture. For a logic signal all trigger events are detected, the logic signal is sampled at a high rate to produce a sampled logic signal data, the sampled logic signal data are delayed to provide a pre-trigger delay and then are drawn in real time in response to the detected trigger events. A FIFO is used to delay the sampled logic signal data, with the position of the trigger event on the display being determined coarsely by an effective depth of the FIFO. The sampled logic signal data may also be compressed into compression codes prior to the FIFO. A fast drawing engine receives the sampled logic signal data from the FIFO as either data samples or compression codes, and draws a logic waveform using four rows of the drawing engine memory—one row for each of four logic states.

Abstract: A method of region overlap control for the display of a plurality of waveforms on an instrument includes an overlap function that allows selection by a user of a vertical height on a display screen for each of the waveforms. A ground marker for each of the waveforms is adjusted on the display screen according to the selected vertical height. The result is that the plurality of waveforms are displayed on the display screen in an overlapping fashion with sufficient vertical height to enhance triggering, all measurement functions and secondary functions, such as harmonics and switching loss measurements.

Abstract: A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demultiplexed into a plurality of multi-bit lanes, such as n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section at a data rate that is optimal for the receiver section. In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.

Abstract: A logic analyzer having clock channels and data channels includes digitizer followed by a digital filter in each channel, the digital filter compensating for losses in signal fidelity in a signal under test. The resulting enhanced multi-bit samples are stored in respective waveform memories for subsequent display as analog waveforms and as logic data. The multi-bit samples from each channel are re-sampled by a regenerated sample clock to determine the logic values of the signal at precise times. For high speed serial data, each channel is divided into multiple clock channels and sampling channels, the outputs from the clock channels being phase adjusted to provide a precise sample clock to the sampling channels and the outputs from the sampling channels being combined to form a serial data output.

Abstract: A method of producing of a two-dimensional probability density function eye diagram and Bit Error Rate eye arrays generates a two-dimensional PDF array of a correlated waveform record of a data pattern under test which is convolved with a two-dimensional probability density function (PDF) array of the uncorrelated jitter and noise in the data pattern under test. The resulting aggregate two dimensional PDF array of the correlated waveform record pattern with uncorrelated jitter and noise is divided into unit intervals and the unit intervals are summed to generated a two-dimensional PDF eye diagram array. The two-dimensional PDF eye diagram is processed to generate a two-dimensional Bit Error Rate eye array.

Abstract: A multi-channel signal acquisition probe has a ribbon cable with ganged coaxial signal cables. The coaxial signal cables are separated into individual cables at one end of the ribbon cable. A junction box is mounted the ribbon cable with the individual cables extending through apertures in a front face of the junction box. An electrically conductive terminal is disposed in the junction box and extends into openings in opposing sides of the junction box. The electrically conductive terminal is electrically coupled to each outer shielding conductor of the signal cables. The free ends of each of the individual signal cables has a probing head. A terminal connector is disposed on the other end of the ribbon cable.

Abstract: A system for simultaneous ACLR measurements encompassing multiple wireless communications channels provides a dual channel processing. The input signal is down converted to produce a wideband signal that is input simultaneously to both a wideband channel having a high speed, low resolution ADC and a narrow band channel having a low speed, high resolution ADC. The resulting data streams from the ADCs are processed by a DSP to provide the simultaneous ACLR measurements.

Abstract: A data processing method is provided to enable a calculation based signal analyzer, such as an FFT based spectrum analyzer, to produce results corresponding to a swept spectrum analyzer employing a video bandwidth (VBW) filter. Once a spectrum is produced the frequency axis is replace by a corresponding time axis, so that a time domain filter, such as a video bandwidth (VBW) filter can be applied. The filter characteristics are applied by performing an FFT to produce frequency domain data, multiplying by the frequency response to produce a filtered version, performing an inverse FFT and replacing the time axis with the original frequency axis to produce a filtered version of the display spectrum data.

Abstract: A trigger generator and trigger method are provided for determining whether or not a signal under test matches a modulation signature. The modulation signature may be provided as a magnitude signature, a phase signature or both. When the magnitude values, phase values, or both of a signal under test are the same as their respective modulation signature, an error computation will be close to zero. If this value is within a threshold value, a trigger signal or other indication of a match is produced.

Abstract: A test and measurement instrument includes a memory configured to store a digitized signal, a display configured to display the digitized signal, a mark interface configured to generate a mark creation signal, a processor coupled to the memory, the display, and the mark interface. The processor is configured to identify a feature of the digitized signal and create a mark indicating the feature and the digitized signal in response to the mark creation signal.

Abstract: A calibration method for an oversampling acquisition system uses a digital calibration signal that has a period between edges that is unrelated to the period of a sample clock. The calibration signal in input in parallel to a plurality of samplers, each of which is clocked at a different time by a delayed version of the sample clock, to produce a plurality of sequential samples per sample clock period. Edge transitions of the calibration signal are counted that occur between adjacent ones of the samplers, and are accrued over an acquisition period to produce a plurality of edge counts. The edge counts are then processed to produce control signals to adjust the sample clock delay for each sampler so that the time intervals between the sequential samples are essentially uniform.

Abstract: Waveform data of selected bits having jitter or noise is generated wherein the waveform date represents a serial digital signal. A signal generator displays a jitter/noise setting area and a bit selection area on a display device where jitter or noise is set and the jitter or noise settings are applied to only the bit selected with the bit selection area. The bit is selected through various ways. A user may directly input a bit pattern to be selected. Box objects corresponding to the respective bits in the digital signal may be displayed and one or more of the bits can be selected by selecting one of the box objects. Frequently used bit patterns may be stored and provided using a menu-driven interface for selecting a bit pattern. An arbitrary number of consecutive bits may be designated for receiving jitter or noise and displayed.

Abstract: A pattern sequence and state transition trigger generator provides a trigger when a specified transition from one pattern/state to another pattern/state occurs in a set of input signals. Decoders detect each specified pattern/state from the set of input signals to produce a prior value and a current value representing the transition. The prior value is slightly delayed and combined with the current value to produce an overlap when the specified transition occurs, which in turn generates the trigger.

Abstract: A system and method is provided enabling identification of different PN offsets values for CDMA signals without access to a GPS signal, such as when making measurements within indoor environments. When a timing reference, such as that provided by a GPS signal, is lost, the frame boundary timestamp of the CDMA signal itself is used. The parameters of the strongest available PN offset are used. The timing error is determined and the new timing reference timestamp is estimated. The strongest PN is used as the time reference and tau is corrected for. In further embodiments, a user may be able to provide identifying information allowing the estimated timing reference timestamp to be determined even when a GPS signal was never established for providing an initial timing reference.

Abstract: Parameters of a spread spectrum clock signal in a communication signal are characterized by acquiring voltage samples of the communication signal at a nominal time location of an edge of the communication signal. The voltage samples are converted to time samples and the difference between the maximum and minimum time values is determined at the nominal time location. A spread spectrum clock magnitude number is generated by dividing the difference between the maximum and minimum time values by the nominal time location of the acquired voltage samples of the spread spectrum clock signal. A spread spectrum modulation profile of a spread spectrum clock signal is estimated by over sampling the time samples using an aliased index value to generate over sampled triangular waveforms representing the spread spectrum clock modulation profile. One of the over sampled triangular waveforms is use to generate the spread spectrum clock modulation profile.

Abstract: A no-reference subjective quality ratings predictor for a lossy compressed signal decodes the lossy compressed signal to produce a decompressed signal, and extracts from the lossy compressed signal error bounding parameters and information data. An error estimation generator converts the error bounding parameters to sensitivity test data which is combined with lossy data from an inverse compression module within the decoder to produce data with bounded errors. The data with bounded errors is converted into a sensitivity decompressed signal. The decompressed and sensitivity decompressed signals are processed by a full-reference subjective quality rating predictor to produce the subjective quality ratings for the lossy compressed signal. The information data and decompressed signal may also be input to the error estimation generator to generate the sensitivity test data in conjunction with the error bounding parameters.

Abstract: A logic analyzer having clock channels and data channels includes digitizer followed by a digital filter in each channel, the digital filter compensating for losses in signal fidelity in a signal under test. The resulting enhanced multi-bit samples are stored in respective waveform memories for subsequent display as analog waveforms and as logic data. The multi-bit samples from each channel are re-sampled by a regenerated sample clock to determine the logic values of the signal at precise times. For high speed serial data, each channel is divided into multiple clock channels and sampling channels, the outputs from the clock channels being phase adjusted to provide a precise sample clock to the sampling channels and the outputs from the sampling channels being combined to form a serial data output.

Abstract: Cooling facilities for an electronic component provide a cooling device that occupies a small volume, requires only a relatively low operating voltage, and operates in any orientation. The cooling facility consists of a body defining a coolant passage including an inlet and an outlet, a pumping chamber with a variable volume changeable from a greater volume to a lesser volume in fluid communication with the inlet and the outlet, and a flow restriction facility in fluid communication with the inlet and the outlet. The flow restriction facility provides limited flow resistance to coolant flow in a first direction from the inlet to the outlet and provides increased resistance to coolant flow in the opposite direction from the outlet to the inlet. Therefore, repeated reciprocation of the pumping chamber between a greater volume and a lesser volume generates a net fluid flow from the inlet to the outlet.

Abstract: An apparatus and method measures the skew between signals on data and clock channels using a bit pattern matching technique for any given protocol in Serial data communication. In one embodiment, the method of finding the pattern comprises of importing the waveform data from the oscilloscope and converting the waveform into bit patterns, finding the pattern index on the converted bit stream using a pattern based on the TMDS channel combination, and then measuring the skew.