Abstract: A first data stream for a first data transmission system having a first data rate contains ATM data cells and structural data, which are distributed as spaced apart data in accordance with a specified instruction and are assigned to a section including in each case a plurality of ATM data cells. While retaining its ATM data cell format, the first data stream is converted into a second data stream containing only ATM data cells for a second data transmission system having a second data rate which is higher than the first data rate. The structural data are thereby selected (or picked out) from the first data stream and are input into a marked structural cell having the ATM cell format, for the section. The structural cell is inserted into the second data stream to partially fill an unoccupied section resulting from the differing data rates.

Abstract: An automatic output offset control circuit for a DC-coupled RF amplified optical-to-electrical converter has a photodiode for converting an optical signal to an electrical signal. The current from one side of the photodiode is coupled into the input of a bipolar RF amplifier that generates a voltage output. The current from the other side of the photodiode is sensed for generating a voltage that is compared with the output of the RF amplifier. Any mismatch between the sensed current and the RF amplifier generates an error signal that is used to control the DC bias supplies of the RF amplifier. The DC bias supplies are adjusted in unison to produce the correct offset at the amplifier output for the given photodiode current while maintaining a constant AC-gain. The circuit automatically corrects for the DC-coupled output offset drift and variations of the RF bipolar amplifier. The circuit may be implemented using either voltage or current signals to the feedback circuit.

Abstract: A highly parallel cyclic redundancy code generator has p precalculated k-bit remainder polynomials loaded in a lookup table. A cyclic redundancy code register has a p-bit portion and a k-bit portion. An input data message is input to an input XOR gate together with the contents of the p-bit portion to generate a p-bit result for storage in the p-bit portion. The content of the p-bit portion is used to control which k-bit remainder polynomials from the lookup table are to be parallel XOR'd to produce a partial cyclic redundancy code that is stored in the k-bit portion. The contents of the CRC register are shifted to the left and the process repeated until all of the bits of the input data message have been processed. The contents of the k-bit portion are then output as the CRC for the input data message.

Abstract: An improved apparatus and method for controlling media temperature to prevent image offset and degloss in an electrostatic image forming apparatus are provided. The apparatus and method utilize a plurality of media support surfaces in the pre-nip media path to reduce heat transfer to the media in this region. An insulating channel is provided beneath the media supports to thermally isolate the media supports. One or more insulating plates may also be provided between the rollers of the fusing nip and the media support surfaces to further reduce heat transfer from the fusing members to the media support surfaces and media.

Abstract: An input expansion for a crosspoint switch module incorporates a plurality of crosspoint switch ICs within the switch module so that the crosspoint switch module may receive a plurality of input differential signals. The crosspoint switch module includes a module driver circuit which, when enabled by a module enable signal, couples a differential current signal to an output. Each crosspoint switch includes an emitter follower configured transistor circuit for receiving one of the input differential signals and providing an output differential signal and a switch transistor circuit configured as a saturated switch for receiving the output differential signal and providing the differential current signal when enabled by a switch enable signal. Only one of the crosspoint switches is enabled at a time so that only one of the crosspoint switches carries current.

Abstract: The present invention provides an ink jet print head capable of fast, efficient and consistent printing. Such ink jet print heads include an ink ejecting component which incorporates electropolished surfaces. Electropolishing techniques useful in the production of such ink ejecting components are also discussed.

Abstract: A duty cycle based AC power control method reduces objectionable voltage fluctuations at a frequency that causes "flicker" by shifting the frequency of actuations of controlled devices to frequencies significantly greater than and/or less than the flicker sensitive frequency. The frequency of actuations may be redistributed (1) by segmenting the devices to provide approximately equal power requirements per actuation, (2) by providing one-half cycle actuation pulses rather than one cycle actuation pulses, and/or (3) by spacing the actuations evenly over a given time period and forcing the aggregate demand to follow a slowly rising/falling envelope. The result is the minimization of power distribution at the flicker frequency.

Abstract: A multiple access record/playback device, such as a digital disk recorder, is used for video effects, such as simultaneously providing a preview video signal and a time offset production video signal of the same video image or simultaneously providing multiple views of the same video image. An input video signal is selected from a plurality of input video signals for storing on the multiple access record/playback device. The input video signal is read out for display from the multiple access record/playback device from an identified start point at two times to provide simultaneously a preview video signal and a time offset production video signal for the same video image.

Abstract: A method for calibrating a printer or other imaging system to accurately place an image on a final receiving substrate is provided. A test image is printed and the margins between the image and the edges of the media are measured. These measured margin values are then utilized to adjust stored calibration factors that calibrate the printer to accurately place the image on the final receiving substrate.

Abstract: The invention concerns a process for detecting the zero crossings of a data signal by employing of a comparator. To be able to accurately detect zero crossings even when the data signal is distorted due to transmission over a system with filtering characteristics, an auxiliary voltage corresponding to half the value of the difference between the measured maximum value of the data signal and the measured minimum value is generated. An additional voltage is formed by comparing a reference quantity that is proportional to the auxiliary voltage with the respective instantaneous value of the data signal and is added to the auxiliary voltage to form a total voltage. The total voltage is used to form the reference voltage of the comparator.

Abstract: An improved ink stick supply assembly is provided for a solid ink color printer which reliability feeds solid ink sticks from an ink stick loading bin to ink stick melt plates which melt the ink sticks on demand and guide the molten ink into individual color ink reservoirs in the printer print head. Low ink and empty ink level sensors are provided which advise the printer operator when to replenish the ink stick supply. A low friction material and spring loaded pusher blocks facilitate travel of the inks through the ink stick feed chutes to the melt plates.

Abstract: A digital audio frame and block synchronization signal is generated from a reference clock having a nominal 50% duty cycle except that one out of every N cycles has a different duty cycle, where N corresponds to a block span of ancillary data within the frame samples of the digital audio. A phase locked loop includes a loop counter that provides a sample clock synchronized with the reference clock. A block counter subdivides the sample clock by N to produce a block clock. A logic circuit has the reference clock and a current count from the loop counter as inputs, and detects when the Nth non-50% duty cycle occurs to generate a reset signal. The reset signal is used to reset the block counter so that the block clock is synchronized with the reference clock.