Abstract: An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.

Abstract: First and second p-type diffusion regions, and first and second n-type diffusion regions are formed in a semiconductor device. Each diffusion region is electrically connected to a common node. Gate electrodes of cross-coupled transistors are defined to extend over the diffusion regions in only a first parallel direction, with each gate electrode fabricated from a respective originating rectangular-shaped layout feature. The first and second p-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. At least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a common line of extent that extends across the substrate perpendicular to the first parallel direction.

Abstract: A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS, second PMOS, first NMOS, and second NMOS transistor devices respectively extend along different gate electrode tracks. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Abstract: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.

Abstract: A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.

Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Abstract: A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths.

Abstract: A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices.

Abstract: A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS, second PMOS, first NMOS, and second NMOS transistor devices respectively extend along different gate electrode tracks. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. The electrical connection between the gate electrodes of the first PMOS and second NMOS transistor devices is formed in part by one or more electrical conductors present within at least one interconnect level above the gate electrode level region.

Abstract: First and second p-type diffusion regions, and first and second n-type diffusion regions are formed in a semiconductor device. Each diffusion region is electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The first and second p-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. At least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a common line of extent that extends across the substrate perpendicular to the first parallel direction.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are different, such that the first and second PMOS transistor devices have different widths. Widths of the first and second n-type diffusion regions are different, such that the first and second NMOS transistor devices have different widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.

Abstract: A semiconductor device includes a substrate having a plurality of diffusion regions defined therein to form first and second p-type diffusion regions, and first and second n-type diffusion regions, with each of these diffusion regions electrically connected to a common node. The first p-type active area and the second p-type active area are contiguously formed together. The first n-type active area and the second n-type active area are contiguously formed together. Gate electrodes are formed from conductive features that are each defined within any one gate level channel. Each gate level channel is uniquely associated with and defined along one of a number of parallel oriented gate electrode tracks. A first PMOS transistor gate electrode is electrically connected to a second NMOS transistor gate electrode, and a second PMOS transistor gate electrode is electrically connected to a first NMOS transistor gate electrode.

Abstract: First and second PMOS transistors are defined over first and second p-type diffusion regions. First and second NMOS transistors are defined over first and second n-type diffusion regions. Each diffusion region is electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.

Abstract: A semiconductor device includes conductive features that are each defined within any one gate level channel uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The gate electrodes include gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.