Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths.

Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions separated by a central inactive region. The cell layout also includes a gate electrode level layout for the entire cell defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal and minimized across the gate electrode level layout. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.

Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: Each of first and second PMOS transistors, and first and second NMOS transistors has a respective diffusion terminal with a direct electrical connection to a common node, and has a respective gate electrode formed from an originating rectangular-shaped layout feature. Centerlines of the originating rectangular-shaped layout features are aligned to be parallel with a first direction. The first PMOS transistor gate electrode is electrically connected to the second NMOS transistor electrode. The second PMOS transistor gate electrode is electrically connected to the first NMOS transistor gate electrode. The first and second PMOS transistors, and the first and second NMOS transistors together define a cross-coupled transistor configuration having commonly oriented gate electrodes formed from respective rectangular-shaped layout features.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication.

Abstract: A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. However, the first PMOS and second NMOS transistor devices are physically separate within the gate electrode level region. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. However, the second PMOS and first NMOS transistor devices are physically separate within the gate electrode level region.

Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level of the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.

Abstract: A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes that define at least one p-type diffusion region and at least one n-type diffusion region separated by a central inactive region. A gate electrode level layout is defined above the diffusion level layout to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A number of PMOS transistor devices is equal to a number of NMOS transistor devices in the restricted layout region. The restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract: A cell of a semiconductor device includes a substrate portion including a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features is fabricated from a respective originating rectangular-shaped layout feature. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. The cell includes an equal number of PMOS and NMOS transistor devices. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A rectangular-shaped interlevel connection structure is defined to electrically connect a first structure in a first chip level with a second structure in a second chip level. The rectangular-shaped interlevel connection structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first structure, the second structure, or both the first and second structures. A dimension of the rectangular-shaped interlevel connection structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines.

Abstract: A set of layout nanopatterns is defined. Each layout nanopattern is defined by relative placements of a particular type of layout feature within a lithographic window of influence. A design space is defined as a set of layout parameters and corresponding value ranges that affect manufacturability of a layout. Layouts are created for the set of layout nanopatterns such that the created layouts cover the design space. The layouts for the set of layout nanopatterns are then optimized for manufacturability. A point in the design space is selected where the set of layout nanopatterns are co-optimized for manufacturability. A circuit layout is created based on the selected point in design space using the corresponding set of co-optimized layout nanopatterns. The optimized layouts for the set of layout nanopatterns and the associated circuit layout can be recorded in a digital format on a computer readable storage medium.

Abstract: Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.

Abstract: First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size.

Abstract: A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within the gate electrode level is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features. The cell also includes a number of interconnect levels formed above the gate electrode level.

Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.