Patents Assigned to Teradyne, Inc.
  • Patent number: 11221365
    Abstract: An example test system includes a device interface board (DIB) having one or more signal transmission paths and an interface for connecting to one or more other components of the test system. Test circuitry is configured to inject test signals into the one or more signal transmission paths and to measure transmitted versions of the test signals at the interface to obtain measurement signals. One or more processing devices are configured to generate calibration factors based on differences between the injected test signals and the measurement signals, and to store the calibration factors in computer memory. The calibration factors are for correcting for effects on the test signals of the one or more signal transmission paths.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: January 11, 2022
    Assignee: Teradyne, Inc.
    Inventors: Stephen J. Lyons, David Tu
  • Patent number: 11221361
    Abstract: An example test system includes an output stage to source at least one of voltage or current to a channel of a test instrument; a tracking circuit to detect a channel voltage following the output stage and to control a supply voltage to the output stage based on the channel voltage; and a controller to determine a power dissipation of the output stage based on the supply voltage and the channel voltage, and to control the output stage based on the power dissipation in the output stage.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 11, 2022
    Assignee: TERADYNE, INC.
    Inventors: Jason A. Messier, Bryce M. Wynn, William Bowhers
  • Patent number: 11215641
    Abstract: Probe pin arrangements in a vertical-type probe card assembly for an automated test equipment (ATE) are disclosed. In some embodiments, one or more additional conductive regions are provided in between adjacent probe pins. The additional conductive regions may reduce spacing between probe pins connected to adjacent probe card pads, and may in turn reduce or adjust inductance between the two probe cards pads to provide improved signal impedance matching or lower power impedance. In one embodiment, the additional conductive region is a short probe pin. In another embodiment, the additional conductive region is a protrusion on a vertical probe pin.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: January 4, 2022
    Assignee: Teradyne, Inc.
    Inventor: Brian Brecht
  • Patent number: 11203116
    Abstract: A computing system is provided for training one or more machine learning models to perform at least a portion of a robotic task of a physical robotic system by monitoring a model-based control algorithm associated with the physical robotic system perform at least a portion of the robotic task. One or more robotic task predictions may be defined, via the one or more machine learning models, based upon, at least in part, the training of the one or more machine learning models. The one or more robotic task predictions may be provided to the model-based control algorithm associated with the physical robotic system. The robotic task may be performed, via the model-based control algorithm associated with the robotic system, on the physical robotic system based upon, at least in part, the one or more robotic task predictions defined by the one or more machine learning models.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: December 21, 2021
    Assignee: TERADYNE, INC.
    Inventors: David Demirdjian, Eric Lenhart Truebenbach
  • Patent number: 11187745
    Abstract: An example method of stabilizing a voltage at a device under test (DUT) includes identifying one or more characteristics of a deviation in a first voltage to appear at the DUT. The deviation may result from a digital signal and a concomitant transient current in the DUT. The digital signal may be part of a test flow to be sent over one or more test channels of automatic test equipment (ATE) to the DUT. The one or more characteristics may be identified prior to sending the test flow to the DUT. The method also includes generating a second voltage to apply to the DUT. The second voltage may be based on the one or more characteristics and being shaped to reduce the deviation.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 30, 2021
    Assignee: TERADYNE, INC.
    Inventors: Jason A. Messier, Bryce M. Wynn, Anja Deric
  • Patent number: 11169203
    Abstract: Example systems for determining a configuration of a test system execute operations that include receiving first parameters specifying at least part of an operation of a test system; receiving second parameters specifying at least part of a first configuration of the test system; determining a second configuration of the test system based, at least in part, on the first parameters and the second parameters, with the second configuration being determined to impact a cost of test of the test system; generating, by one or more processing devices, data for a graphical user interface representing information about the second configuration and the cost of test; and outputting the data for the graphical user interface for rendering on a display device.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: November 9, 2021
    Assignee: TERADYNE, INC.
    Inventor: Randall T. Kramer
  • Patent number: 11162980
    Abstract: A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a probe card having ground vias in a coaxial arrangement around a signal via that provide electromagnetic shielding to a signal via to reduce crosstalk between adjacent signal vias.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: November 2, 2021
    Assignee: Teradyne, Inc.
    Inventor: Brian Brecht
  • Patent number: 11159248
    Abstract: An example optical receiving device includes a photodiode to receive an optical signal, where the photodiode is configured to conduct a current that is based on an optical power of the optical signal, and a radio frequency (RF) gain circuitry to generate one or more analog electrical signals based on the current and based on gain provided by the RF gain circuitry. A power detector is configured to receive an analog electrical signal of the one or more analog electrical signals, to detect alternating current (AC) power of the optical signal based on the analog electrical signal, and to output a signal representing the AC power based on the detecting.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 26, 2021
    Assignee: TERADYNE, INC.
    Inventors: Tushar K. Gohel, Thomas D. Jacobs
  • Patent number: 11156692
    Abstract: Example circuitry includes a first circuit to provide a low signal; a second circuit to provide a high signal, where the high signal has a greater voltage magnitude than the low signal; and a differential amplifier configured to receive the low signal from the first circuit and the high signal from the second circuit. The differential amplifier is for producing an output voltage that is based on the high signal and the low signal. The example circuitry includes a first measurement circuit to measure the output voltage; a second measurement circuit to measure the low signal at the first circuit; and processing logic to determine a differential measurement based on the output voltage measured by the first measurement circuit, the low signal measured by the second measurement circuit, and calibration values obtained for the circuitry.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 26, 2021
    Assignee: TERADYNE, INC.
    Inventor: Igor Golger
  • Patent number: 11119155
    Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice has a time constant, and is controlled to switchably connect a driver output to either a high voltage level or a low voltage level, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. The circuit slices may also have programmable capacitors that may be adjusted to provide a programmable time domain behavior of the output voltage waveform, such as a programmable voltage peaking characteristic.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 14, 2021
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Allan Parks, Lawrence Choi
  • Patent number: 11103994
    Abstract: Embodiments of the present disclosure are directed towards a robotic system and method, which may include one or more robots. The system may include a robotic system having a maximum number of degrees of freedom. The system may further include a graphical user interface configured to receive a natural robot task having at least one natural workpiece constraint associated with the natural robot task. The system may also include a processor configured to identify a minimum number of degrees of freedom required to perform the natural robot task, wherein the minimum number of degrees of freedom is based upon, at least in part, the at least one natural workpiece constraint associated with the natural robot task.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: August 31, 2021
    Assignee: Teradyne, Inc.
    Inventors: Brett L. Limone, Justin C. Keesling, Chalongrath Pholsiri, James D. English, Chu-Yin Chang
  • Patent number: 11092654
    Abstract: The systems determine the parasitic capacitance of a signal path. That parasitic capacitance is then used to determine a leakage characteristic of the signal path, such as leakage current or leakage resistance. The capability of ATE channels to force current accurately, and to measure time intervals at prescribed voltages, can be used to multiply the accuracy of the force current function. Using these resources, small leakage currents—for example, on the order of 10 nA or less—can be measured.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 17, 2021
    Assignee: Teradyne, Inc.
    Inventor: Marc Spehlmann
  • Patent number: 11067629
    Abstract: Aspects of the present application are directed to an automated test equipment (ATE) and methods for operating the same for testing high-power electronic components. The inventor has recognized and appreciated an ATE that provides both high-power alternating-current (AC) and direct-current (DC) testing in a single test system can lead to high throughput testing for high-power components with reduced system hardware complexity and cost. Aspects of the present application provide a synchronized inductor switch module and both a high-precision digitizer and a high-speed digitizer for capturing DC and AC characteristics of a high-power transistor.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 20, 2021
    Assignee: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Publication number: 20210190825
    Abstract: A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a probe card having ground vias in a coaxial arrangement around a signal via that provide electromagnetic shielding to a signal via to reduce crosstalk between adjacent signal vias.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Applicant: Teradyne, Inc.
    Inventor: Brian Brecht
  • Publication number: 20210190828
    Abstract: A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a transposed via arrangement within a circuit board for a probe card, where adjacent vias are offset towards each other such that the inductance between the adjacent vias may be reduced to provide a desirable impedance during high frequency signal and/or power transmission.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Applicant: Teradyne, Inc.
    Inventor: Brian Brecht
  • Publication number: 20210190826
    Abstract: A probe card in an automated test equipment (ATE) and methods for operating the same for testing electronic devices. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins. The probe card has a pad geometry that compensates for misalignment with corresponding probe pins due to manufacturing error or a mismatch of coefficient of thermal expansion, enabling reliable operation of the ATE over a wide range of test temperatures. The pad array may have a plurality of elongated pads, each of uniquely designed size, tilt angle, and/or center location, with the characteristics of each pad being dependent on a distance between each pad and a centroid of the pad array, such that a probe pin to pad location errors can be mitigated.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Applicant: Teradyne, Inc.
    Inventors: Brian Brecht, Steve Ledford
  • Publication number: 20210190827
    Abstract: Probe pin arrangements in a vertical-type probe card assembly for an automated test equipment (ATE) are disclosed. In some embodiments, one or more additional conductive regions are provided in between adjacent probe pins. The additional conductive regions may reduce spacing between probe pins connected to adjacent probe card pads, and may in turn reduce or adjust inductance between the two probe cards pads to provide improved signal impedance matching or lower power impedance. In one embodiment, the additional conductive region is a short probe pin. In another embodiment, the additional conductive region is a protrusion on a vertical probe pin.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Applicant: Teradyne, Inc.
    Inventor: Brian Brecht
  • Patent number: 11041900
    Abstract: A test system and test techniques for accurate high-current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 22, 2021
    Assignee: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Patent number: 10996272
    Abstract: An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second circuit input; a circuit path to provide a signal to the first circuit input; and a delay element connected to the circuit path and to the second circuit input.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 4, 2021
    Assignee: TERADYNE, INC.
    Inventor: Jan Paul Antonie van der Wagt
  • Patent number: D938960
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 21, 2021
    Assignee: TERADYNE, INC.
    Inventors: Eric Lenhart Truebenbach, Chris Behling, Peter Lustig