Abstract: Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal-oxide-semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.

Abstract: Disclosed herein are voltage driver circuits and methods of operating the same to provide a variable output voltage that is suitable for use in ATE to provide a large number of test signals with accurate voltage levels at high data rates using components that consume relatively low power. According to an aspect, a change in output current in a voltage driver related to changing output voltage may be offset by a stabilization current generated by a correction driver for the voltage driver, such that supply currents drawn from the supply voltages can remain substantially stable. The correction driver may be connected to one or more supply voltages, and programmed to output a stabilization current that offsets changes in supply currents arising from changing of the programmed output of the voltage driver circuit. Such a driver may enable a test system to more precisely test semiconductor devices.

Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice has a time constant, and is controlled to switchably connect a driver output to either a high voltage level or a low voltage level, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. The circuit slices may also have programmable capacitors that may be adjusted to provide a programmable time domain behavior of the output voltage waveform, such as a programmable voltage peaking characteristic.

Abstract: Automatic test equipment with multiple components to generate highly accurate and stable analog test signals and method for operating the test system in semiconductor manufacturing process are disclosed. Output analog signals from existing test systems often fail the stability and accuracy requirement with less than 10 mV variations for testing certain electronic devices, due in part to environmental condition variations such as temperature fluctuations. Traditional compensation mechanisms for temperature variations involve time consuming and disruptive calibration procedures. Disclosed here is a system and method that provides near real-time monitoring and compensation for temperature-induced variations via a digital control mechanism that compensates for environmental variations in a time scale of less than 10 milliseconds and maintains the AC output analog signal with 10 milliVolt accuracy.

Abstract: In general, a test instrument includes a first processing system that is programmable to run one or more test programs to test a device interfaced to a test instrument, and that is programmed to control operation of the test instrument, and a second processing system that is dedicated to device testing. The second processing system being programmable to run one or more test programs to test the device, and the first processing system has a first application programming interface (API) and the second processing system has a second API, the first API and the second API being different APIs, the first API and the second API having at least some duplicate functions.

Abstract: An example test system includes a test carrier to receive a device to test. The test carrier includes test components to perform at least a structural test on the device. The example test system also includes a slot to receive the test carrier. The slot includes an interface to which the test carrier connects to enable the test carrier to communicate with a system that is part of the test system or external to the test system.

Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice is controlled to switchably connect a driver output to either a high voltage level or a low voltage level via a resistor, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. A calibration procedure is disclosed herein to generate a lookup table for how to selectively connect circuit slices to supply voltages given a target output voltage.

Abstract: An example method determines an error vector magnitude using automatic test equipment (ATE). The method includes demodulating data received at a first receiver to produce first symbol error vectors, where each first symbol error vector represents a difference between a predefined point on a constellation diagram and a first measured point on the constellation diagram generated based on at least part of the data received by the first receiver; demodulating the data received at a second receiver to produce second symbol error vectors, where each second symbol error vector represents a difference between the predefined point on the constellation diagram and a second measured point on the constellation diagram generated based on at least part of the data received by the second receiver; and determining the error vector magnitude for the data based on the first symbol error vectors and the second symbol error vectors.

Abstract: An example test system includes: a test rack including test slots; first and second shuttles that are configured to move contemporaneously to transport devices towards and away from trays, with at least some of the devices having been tested and at least some of the devices to be tested; first and second robots that are configured to move contemporaneously to move the devices that have been tested from test sockets in test carriers to the first and second shuttles, and to move the devices to be tested from the first and second shuttles to the test sockets in test carriers; and first and second test arms that are configured to move contemporaneously to move the test carriers between the first and second robots and the test rack.

Abstract: An example system includes non-transitory machine-readable storage storing calibration data sets. A calibration data set includes parameter values that vary non-linearly. Each of the calibration data sets is temperature-specific. The example system also includes channels over which signals pass to and from units under test (UUTs). A channel includes input circuitry to receive a signal of the signals and to obtain a first parameter based on the signal; and correction circuitry to obtain a second parameter based on the first parameter and based on the calibration data set. The second parameter includes a calibrated version of the first parameter. The calibration data set is selectable based on temperature.

Abstract: A test system and test techniques for accurate high current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.

Abstract: An example test system has resources that are distributed for access by a device under test (DUT). The example test system includes a device interface board (DIB) having sites to connect to devices to test, and a tester having slots configured to hold test instruments. Each test instrument has resources that are distributed over a dimension of the DIB. The resources are distributed to enable the devices in the sites equal access to the resources.

Abstract: Apparatus and methods for detecting and identifying a cause of a hot-switching event in an automated test system. One or more antennae positioned near mechanical relays in the system may be used to sense electromagnetic radiation. The antennae may be configured to respond to electromagnetic radiation of the type generated during a hot-switching event. Signals measured by the antennae may be processed to determine whether the signals have characteristics of hot-switching events. Processing may entail generating a signal envelope and determining whether the envelope has characteristics indicative of a hot-switching event. When a hot-switching event is detected, information to correlate the event to other events in the test system may also be captured. That information may be time information, enabling program test-system program instructions executing at the time of the event to be identified, such that the test system may be reprogrammed to avoid hot-switching events.

Abstract: Apparatus and methods for detecting and identifying a cause of a hot-switching event in an automated test system. One or more antennae positioned near mechanical relays in the system may be used to sense electromagnetic radiation. The antennae may be configured to respond to electromagnetic radiation of the type generated during a hot-switching event. Signals measured by the antennae may be processed to determine whether the signals have characteristics of hot-switching events. Processing may entail generating a signal envelope and determining whether the envelope has characteristics indicative of a hot-switching event. When a hot-switching event is detected, information to correlate the event to other events in the test system may also be captured. That information may be time information, enabling program test-system program instructions executing at the time of the event to be identified, such that the test system may be reprogrammed to avoid hot-switching events.

Abstract: An example process includes: powering, via a power supply, an active-matrix display panel comprised of picture elements; and identifying, based on an output of the power supply, one or more picture elements in the active-matrix display panel that are potentially defective. The example process may also include identifying, among one or more of the picture elements that are potentially-defective, one or more picture elements that actually are defective.

Abstract: Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.

Abstract: An example process for aligning channels in automatic test equipment (ATE) includes programming a first delay associated with receiving first data over a channel so that timing of the channel is aligned to timings of other channels in the ATE; programming a second delay associated with a driver driving second data over the channel based on receipt of an edge of the second data so that timing of the second data is aligned to the timing of the channel; and programming a third delay associated with a signal to enable the driver to drive the second data over the channel, with the third delay being programmed to align timing of the signal to the timing of the channel, and with the third delay being based on an edge that corresponds to an edge of the signal created by controlling operation of the driver.

Abstract: An example system includes capture circuitry to obtain first parametric data based on a first signal at an interface to a first communication channel, with the first parametric data representing non-informational content of the first signal; and control circuitry to receive the first parametric data and to provide second parametric data, the second parametric data being based on one or both of: the first parametric data or a programmatic input. The example system also includes interface circuitry to receive the second parametric data and to receive informational content data representing informational content, and to process the informational content data and the second parametric data to produce a second signal. The second signal has the informational content represented by the informational content data and having at least some non-informational content based on the second parametric data.

Abstract: Example automatic test equipment (ATE) includes: a per-pin measurement unit (PPMU); logic configured to execute a state machine to control the PPMU; memory that is part of, or separate from, the logic; and a control system to command the logic; where, in response to a command from the control system, the state machine is configured to obtain, at a known interval or ATE event, data that is based on an output of a measurement by the PPMU and to store the data in the memory, or to output data to the PPMU from the memory at a known interval or synchronous to an event.

Abstract: An example system includes a circuit board having electrical elements; a wafer having contacts; and an interconnect to route signals between the electrical elements and the contacts. The interconnect includes multiple layers, each of which includes a flexible circuit. The flexible circuit includes a conductive trace disposed thereon. The interconnect also includes shielding between adjacent layers of the multiple layers. The shielding is electrically connected to ground.