Abstract: Resistive random-access memory (RRAM) devices for high-temperature applications and methods for fabricating the same are provided. An RRAM device may include a first electrode, a switching oxide layer comprising a switching oxide, and a second electrode. The switching oxide may be HfOx, TaOy, ZrOz, etc. The first electrode comprises a first electrode material that is non-reactive to the switching oxide and presents high thermal stability, such as platinum (Pt), iridium (Ir), palladium (Pd), carbon, chromium (Cr), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), or a conductive ceramic. The second electrode comprises a second electrode material that is reactive to the switching oxide, such as tantalum (Ta), hafnium (Hf), tungsten (W), molybdenum (Mo), zirconium (Zr), or niobium (Nb). The RRAM device may further include one or more interface layers positioned between the first electrode and/or the second electrode and the switching oxide layer and/or embedded within the switching oxide layer.

Abstract: The present disclosure provides memristor-based crossbar circuits. A crossbar circuit may include a crossbar array of cross-point devices connecting to intersecting word lines and bit lines. The crossbar circuit further includes a first readout circuit configured to generate an output voltage representing a sum of currents flowing through a bit line connecting to one or more of the cross-point devices. The crossbar circuit further includes a voltage replica circuit connected to the first readout circuit. The voltage replica circuit includes a replica cell configured to produce a reference cell current, an operational amplifier, and a second readout circuit connected to the replica cell and the operational amplifier. The output of the operational amplifier is connected to the first readout circuit to provide a bias voltage to the first readout circuit.

Abstract: The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of cross-point devices, and one or more first capacitors operatively connected to the plurality of bit lines. Each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines. The crossbar circuit may further include one or more second capacitors operatively connected to the plurality of word lines. The crossbar circuit may further include a plurality of select lines and/or one or more third capacitors operatively connected to the select lines.

Abstract: The present disclosure provides for computing systems incorporating high bandwidth in-memory computing stacks. A computing system may include a processing die and a magneto-resistive random-access memory (MRAM) stack connected to an interposer. The MRAM stack may include a plurality of vertically stacked MRAM dies for performing non-volatile memory and/or in-memory computing. Each of the MRAM dies may include one or more crossbar arrays configured to perform non-volatile memory and/or in-memory computing. Each of the plurality of crossbar arrays may include a plurality of bit lines, a plurality of word lines, and a plurality of cross-point devices at intersections of the plurality of word lines and the plurality of bit lines. Each of the cross-point devices may include one or more MRAM devices. In some embodiments, the computing system may further include vertically stacked dynamic random-access memory (DRAM) arrays, flash memory arrays. and/or resistive random-access memory (RRAM) arrays.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode comprising a metal nitride; a second electrode comprising a first conductive material; and a switching oxide layer positioned between the first electrode and the second electrode. The switching oxide layer comprises at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and/or tantalum nitride. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.

Abstract: The present disclosure provides for computing systems incorporating high bandwidth in-memory computing stacks. A computing system may include a processing die and an RRAM stack connected to an interposer. The RRAM stack may include a plurality of vertically stacked RRAM dies for performing non-volatile memory, multi-level memory, and/or in-memory computing. Each of the RRAM dies may include one or more crossbar arrays configured to perform non-volatile memory and/or in-memory computing. Each of the plurality of crossbar arrays may include a plurality of bit lines, a plurality of word lines, and a plurality of cross-point devices at intersections of the plurality of word lines and the plurality of bit lines. In some embodiments, the computing system may further include vertically stacked dynamic random-access memory (DRAM) arrays and/or flash memory arrays.

Abstract: The present disclosure provides resistive random-access memory (RRAM) devices and methods for making the same. An RRAM device may include a first electrode, a second electrode comprising a ruthenium alloy, and a switching oxide layer fabricated between the first electrode and the second electrode. The first electrode may include palladium, tungsten, nickel, titanium nitride, tantalum nitride, etc. The switching oxide layer may include at least one transition metal oxide. The ruthenium alloy may include a binary ruthenium alloy, such as a platinum-ruthenium alloy, an iridium-ruthenium alloy, an osmium-ruthenium alloy, a rhodium-ruthenium alloy, a molybdenum-ruthenium alloy, a chromium-ruthenium alloy, an iron-ruthenium alloy, or a tantalum-ruthenium alloy. In some embodiments, the RRAM device may further have an interface layer positioned between the switching oxide layer and the second electrode and/or an interface layer positioned between the first electrode and the switching oxide layer.

Abstract: Methods for enhanced error correction code for error detection and correction in multi-level cell-based memory devices are provided. The methods include receiving, at an error correction code (ECC) decoder hardware device, data encoded with ECC information from a multi-level cell-based memory device; calculating an error value and an error location for an error in the data using Reed-Solomon (RS) error correction code (ECC); determining an error type of the error, wherein the error type comprises one of no error, a single symbol error in the data, or multiple symbol errors in the data, and wherein determining the error type is based on a +1/?1 error constraint; and responsive to the error type comprising multiple symbol errors, repeating a read of the data from the multi-level cell-based memory device.

Abstract: Switching oxide engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. A method for fabricating a crossbar device may include forming a bottom electrode on a substrate, forming a switching oxide stack on the bottom electrode, and forming a top electrode on the switching oxide stack. Fabricating the switching oxide stack may include fabricating a plurality of base oxide layers and a plurality of discontinuous oxide layers alternately stacked, wherein the base oxide layers comprise one or more base oxides, wherein the one or more base oxides comprise at least one of TaOx, HfOx, TiOx, or ZrOx.

Abstract: The present disclosure provides methods for programming multilevel memory devices. The methods may include determining a first plurality of memory windows representative of gaps between dispersions of adjacent conductance states of the memory device, determining a plurality of dispersion parameters representative of estimated dispersions of the conductance states, and determining a second plurality of memory windows based on the first plurality of memory windows and the plurality of dispersion parameters. The second plurality of memory windows represents separations between mean conductance values of adjacent conductance states of the memory device. The second plurality of memory windows has varying values.

Abstract: In some embodiments, an apparatus for performing convolution operations is provided. The apparatus may include multiple crossbar arrays and select circuits. The select circuits are configured to select a first plurality of cross-point devices and a second plurality of cross-point devices in response to receiving a control signal indicating that a regular convolution is to be performed, and to select the first plurality of cross-point devices and a third plurality of cross-point devices in response to receiving a control signal indicating that a depthwise convolution is to be performed. The first plurality of cross-point devices is connected to a first plurality of word lines and a first bit line. The second plurality of cross-point devices is connected to the first plurality of word lines and a second bit line. The third plurality of cross-point devices is connected to a second plurality of word lines and the second bit line.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. An RRAM device may include a first electrode, an interface layer fabricated on the first electrode, a switching oxide layer comprising at least one transition metal oxide; and a second electrode fabricated on the switching oxide layer. The interface layer may include a discontinuous layer of a dielectric material and a conductive material deposited in the discontinuous layer of the dielectric material. The interface layer is positioned between the first electrode and the switching oxide layer. The dielectric material may be and/or include Al2O3, SiO2, Si3N4, MgO, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, La2O3, etc. The conductive material may include a metal, a conductive oxide, a conductive nitride, etc.

Abstract: The present disclosure relates to memristor devices for neuromorphic computing. A memristor device may include a first electrode, a switching oxide layer, and a second electrode fabricated on the interface layer. The first electrode may include a noble metal and/or an inert metal, such as platinum, palladium, iridium, tungsten, molybdenum, ruthenium, etc. The switching oxide layer may include a polycrystalline oxide. The polycrystalline oxide may be a base oxide (e.g., silicon dioxide, hafnium dioxide, tantalum pentoxide, etc.) doped with Cu, CuO, Cu2O, etc. The second electrode may include one or more metallic materials that may provide metal ions in response to the application of a suitable voltage to the memristor device, such as copper, silver, etc.

Abstract: The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.

Abstract: Methods for enhanced error correction code for error detection and correction in multi-level cell-based memory devices are provided. The methods include receiving, at an error correction code (ECC) decoder hardware device, data encoded with ECC information from a multi-level cell-based memory device; calculating an error value and an error location for an error in the data using Reed-Solomon (RS) error correction code (ECC); determining an error type of the error, wherein the error type comprises one of no error, a single symbol error in the data, or multiple symbol errors in the data, and wherein determining the error type is based on a +1/?1 error constraint; and responsive to the error type comprising multiple symbol errors, repeating a read of the data from the multi-level cell-based memory device.

Abstract: The present disclosure provides a crossbar circuit for performing in-memory computing and methods for performing vector-matrix multiplication (VMM) using the crossbar circuit. The crossbar circuit may include crossbar subarrays, trans-impedance amplifiers (TIAs), and analog-to-digital converter (ADCs). The crossbar subarrays may be programmed sequentially to compensate for residual errors associated with the previously programmed crossbar subarrays. For example, a first crossbar subarray may be programmed based on target conductance values. A second crossbar subarray may then be programmed based on the programming error associated with the first crossbar subarray. After the programming of the crossbar subarrays, input signals representative of an input matrix may be applied to the programmed crossbar subarrays. The TIAs may generate output voltages representative of accumulated current on the bit lines of the programmed crossbar subarrays.

Abstract: The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.

Abstract: The present disclosure provides read-out circuits for crossbar circuits. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines and a plurality of cross-point devices. Each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines. The crossbar circuit may further include an output sensor that generates a digital output representative of a sum of currents flowing through one or more bit lines of the crossbar circuit. The output sensor includes a first transistor serially connected to a second transistor and an analog-to-digital converter configured to output the digital output. The read-out circuit is an open loop circuit. The read-out circuit may be selectively connected to one of the plurality of bit lines to perform a read operation.

Abstract: An apparatus may include a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of cross-point devices connecting to the bit lines, the word lines, and the source lines. A first cross-point device of the plurality of cross-point devices is connected to a first bit line and a second bit line of the plurality of bit lines, a first word line of the plurality of word lines, and a first source line of the plurality of source lines. The first cross-point device may include a first RRAM device, an NMOS transistor connected to the first RRAM device, a PMOS transistor connected to the NMOS transistor, and a second RRAM device connected to the PMOS transistor. The NMOS transistor and the PMOS transistor are connected to the first source line and can be arranged in a side-by-side structure or a stacked-up structure.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating an RRAM device includes: fabricating a first bottom electrode and a second bottom electrode on a substrate; fabricating a first isolation layer on the substrate, the first bottom electrode, and the second bottom electrode; fabricating a via in the first isolation layer to expose a portion of the first bottom electrode; fabricating a switching oxide layer on the first isolation layer and the exposed portion of the first bottom electrode; and fabricating a filament-forming layer by etching a portion of the switching oxide layer that extends beyond the via. The portion of the switching oxide layer does not contact the exposed portion of the first bottom electrode. A top electrode is fabricated on the filament-forming layer. A top metal interconnect may be fabricated on the top electrode and a second isolation layer.