Abstract: The present disclosure relates to memristor devices for neuromorphic computing. A memristor device may include a first electrode, a switching oxide layer, and a second electrode fabricated on the interface layer. The first electrode may include a noble metal and/or an inert metal, such as platinum, palladium, iridium, tungsten, molybdenum, ruthenium, etc. The switching oxide layer may include a polycrystalline oxide. The polycrystalline oxide may be a base oxide (e.g., silicon dioxide, hafnium dioxide, tantalum pentoxide, etc.) doped with Cu, CuO, Cu2O, etc. The second electrode may include one or more metallic materials that may provide metal ions in response to the application of a suitable voltage to the memristor device, such as copper, silver, etc.

Abstract: The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.

Abstract: Methods for enhanced error correction code for error detection and correction in multi-level cell-based memory devices are provided. The methods include receiving, at an error correction code (ECC) decoder hardware device, data encoded with ECC information from a multi-level cell-based memory device; calculating an error value and an error location for an error in the data using Reed-Solomon (RS) error correction code (ECC); determining an error type of the error, wherein the error type comprises one of no error, a single symbol error in the data, or multiple symbol errors in the data, and wherein determining the error type is based on a +1/?1 error constraint; and responsive to the error type comprising multiple symbol errors, repeating a read of the data from the multi-level cell-based memory device.

Abstract: The present disclosure provides a crossbar circuit for performing in-memory computing and methods for performing vector-matrix multiplication (VMM) using the crossbar circuit. The crossbar circuit may include crossbar subarrays, trans-impedance amplifiers (TIAs), and analog-to-digital converter (ADCs). The crossbar subarrays may be programmed sequentially to compensate for residual errors associated with the previously programmed crossbar subarrays. For example, a first crossbar subarray may be programmed based on target conductance values. A second crossbar subarray may then be programmed based on the programming error associated with the first crossbar subarray. After the programming of the crossbar subarrays, input signals representative of an input matrix may be applied to the programmed crossbar subarrays. The TIAs may generate output voltages representative of accumulated current on the bit lines of the programmed crossbar subarrays.

Abstract: The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.

Abstract: The present disclosure provides read-out circuits for crossbar circuits. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines and a plurality of cross-point devices. Each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines. The crossbar circuit may further include an output sensor that generates a digital output representative of a sum of currents flowing through one or more bit lines of the crossbar circuit. The output sensor includes a first transistor serially connected to a second transistor and an analog-to-digital converter configured to output the digital output. The read-out circuit is an open loop circuit. The read-out circuit may be selectively connected to one of the plurality of bit lines to perform a read operation.

Abstract: An apparatus may include a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of cross-point devices connecting to the bit lines, the word lines, and the source lines. A first cross-point device of the plurality of cross-point devices is connected to a first bit line and a second bit line of the plurality of bit lines, a first word line of the plurality of word lines, and a first source line of the plurality of source lines. The first cross-point device may include a first RRAM device, an NMOS transistor connected to the first RRAM device, a PMOS transistor connected to the NMOS transistor, and a second RRAM device connected to the PMOS transistor. The NMOS transistor and the PMOS transistor are connected to the first source line and can be arranged in a side-by-side structure or a stacked-up structure.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating an RRAM device includes: fabricating a first bottom electrode and a second bottom electrode on a substrate; fabricating a first isolation layer on the substrate, the first bottom electrode, and the second bottom electrode; fabricating a via in the first isolation layer to expose a portion of the first bottom electrode; fabricating a switching oxide layer on the first isolation layer and the exposed portion of the first bottom electrode; and fabricating a filament-forming layer by etching a portion of the switching oxide layer that extends beyond the via. The portion of the switching oxide layer does not contact the exposed portion of the first bottom electrode. A top electrode is fabricated on the filament-forming layer. A top metal interconnect may be fabricated on the top electrode and a second isolation layer.

Abstract: The present disclosure relates to crossbar circuits utilizing resistive random-access memory (RRAM) devices. A crossbar circuit may include a plurality of word lines intersecting with a plurality of bit lines, and a plurality of cross-point devices. Each of the cross-point devices is connected to one of the word lines and one of the bit lines and includes a resistive random-access memory (RRAM) device. The crossbar circuit may further include one or more current digital-to-analog converters (IDACs) configured to perform digital-to-analog conversion. The IDACs are selectively connected to the word lines or the bit lines to provide programming signals to program the RRAM devices to predetermined conductance values. The IDACs may linearly control the compliance currents of the RRAM devices to program the RRAM devices to multiple linearly separated conductance values.

Abstract: An apparatus including a CMOS-compatible resistive random-access memory (RRAM) device is provided. An RRAM device may include a bottom electrode, a switching oxide device comprising at least one transition metal oxide, a via structure fabricated on the switching oxide device, and a top electrode fabricated within the via structure and over a top surface of the via structure. The via structure comprises a via fabricated in a hard mask layer. The RRAM device may further include a first spacer encapsulating the top electrode and the hard mask layer. In some embodiments, the RRAM device may further include a second spacer encapsulating the first spacer, the bottom electrode, and the switching oxide device.

Abstract: In accordance with some embodiments of the present disclosure a tunneling-based selector is provided. The selector includes a multilayer barrier structure fabricated between a first electrode and a second electrode. The multilayer barrier structure includes a first layer of a first van der Waals (vdW) material; a second layer of a second vdW material; and a third layer of a third vdW material. The first layer of the first vdW material is fabricated between the second layer of the second vdW material and the third layer of the third vdW material. The electron affinity of the first layer of the first vdW material is lower than the second electron affinity of the second layer of the second vdW material and the electron affinity of the third layer of the vdW material.

Abstract: The present disclosure provides methods for programming multilevel memory devices. The methods may include determining a first plurality of memory windows representative of gaps between dispersions of adjacent conductance states of the memory device, determining a plurality of dispersion parameters representative of estimated dispersions of the conductance states, and determining a second plurality of memory windows based on the first plurality of memory windows and the plurality of dispersion parameters. The second plurality of memory windows represents separations between mean conductance values of adjacent conductance states of the memory device. The second plurality of memory windows has varying values.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating resistive random-access memory (RRAM) device may include fabricating, on a first electrode of the RRAM device, a first interface layer comprising a first discontinuous film of a first material; fabricating, on the first interface layer, a switching oxide layer comprising at least one transition metal oxide; fabricating a second interface layer on the switching oxide layer; and fabricating a defect engineering layer on the second interface layer. The first material is more chemically stable than the at least one transition metal oxide. The defect engineering layer includes a layer of Ti in some embodiments.

Abstract: Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.

Abstract: A crossbar circuit is provided. The crossbar circuit includes one or more bit lines, one or more word lines, one or more cell devices connected between the bit lines and the word lines, one or more analog-to-digital converters (ADCs) connected to the one or more bit lines, one or more digital-to-analog converters (DACs) connected to the one or more word lines, one or more access controls connected to the one or more cell devices and configured to select a cell device in the one or more cell devices and to program the selected cell device, and a slew rate controller connected to the one or more bit lines. The first slew rate controller is configured to receive an input signal or a bias and output a slew-rate controlled signal.

Abstract: A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

Abstract: The present disclosure relates to memristor devices for neuromorphic computing. A memristor device may include a first electrode, an oxide layer, an interface layer fabricated on the oxide layer, and a second electrode fabricated on the interface layer. The first electrode may include a noble metal and/or an inert metal, such as platinum, palladium, iridium, tungsten, molybdenum, ruthenium, etc. The oxide layer may include a dielectric oxide, such as silicon dioxide, hafnium dioxide, tantalum pentoxide, etc. The interface layer may include a discontinuous layer of a  dielectric material,  such as Al2O3, Y2O3, MgO, etc. The second electrode may include one or more metallic materials that may provide metal ions in response to the application of a suitable voltage to the memristor device, such as copper, silver, etc. In some embodiments, the memristor device may further include an interface layer positioned between the first electrode and the oxide layer.

Abstract: In accordance with some embodiments of the present disclosure, a memory device is provided. The memory may include a ferroelectric layer including a ferroelectric material interstitially doped with at least one interstitial dopant. The ferroelectric material may include a metal oxide. The interstitial dopant may include an element having an atomic radius that is not greater than an atomic radius of a metal element of the metal oxide. In some embodiments, the metal oxide comprises at least one of hafnium or zirconium. The memory device may be non-volatile. The memory device may be a ferroelectric capacitor (FeCAP), a ferroelectric field-effect transistor (FeFET), a ferroelectric tunneling junction (FTJ), and/or another form of ferroelectric random-access memory (Fe-RAM).

Abstract: Methods for programming crossbar circuits are provided. The methods include initializing a word line voltage, a bit line voltage, and a select voltage applied to a cross-point device of the crossbar circuit. The methods further include raising the word line voltage without changing the bit line voltage. The bit line voltage may be raised without changing the word line voltage applied to the cross-point device. The word line voltage and the bit line voltage may be alternatively changed until they reach their respective desired values. In some embodiments, the methods further include setting the bit line voltage to a predetermined value and raising the word line voltage without changing the select voltage. The select voltage may then be raised without changing the word line voltage applied to the cross-point device. The word line voltage and the select voltage may be alternatively changed until they reach their respective desired values.

Abstract: The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.