Abstract: Methods for programming crossbar circuits are provided. The methods include initializing a word line voltage, a bit line voltage, and a select voltage applied to a cross-point device of the crossbar circuit. The methods further include raising the word line voltage without changing the bit line voltage. The bit line voltage may be raised without changing the word line voltage applied to the cross-point device. The word line voltage and the bit line voltage may be alternatively changed until they reach their respective desired values. In some embodiments, the methods further include setting the bit line voltage to a predetermined value and raising the word line voltage without changing the select voltage. The select voltage may then be raised without changing the word line voltage applied to the cross-point device. The word line voltage and the select voltage may be alternatively changed until they reach their respective desired values.

Abstract: A method for forming a crossbar circuit is provided. The method may include forming a Resistive Random-Access Memory (RRAM) stack on a first line electrode and a substrate, forming an isolation layer on the first line electrode and the RRAM stack, etching the isolation layer to expose a top surface of the RRAM stack, and forming a selector stack on the top surface of the RRAM stack, a sidewall of the isolation layer, and an upper surface of the isolation layer. The method may further include forming a second line electrode on the selector stack.

Abstract: According to some aspects of the disclosure, a crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of cross-point devices, and a plurality of switches connected to the plurality of word lines. Each of the plurality of cross-point devices is connected to at least one of the word lines and at least one of bit lines and may include a resistive random-access memory (RRAM) device. Each of the switches is selectively connected to ground or a reference voltage. A digital input may be provided to a cross-point device of the crossbar circuit by selectively connecting a word line connected to the cross-point device to ground or the reference voltage.

Abstract: The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.

Abstract: Systems and methods for mitigating defects in a crossbar-based computing environment are disclosed. In some implementations, an apparatus comprises: a plurality of row wires; a plurality of column wires connecting between the plurality of row wires; a plurality of non-linear devices formed in each of a plurality of column wires configured to receive an input signal, wherein at least one of the non-linear devices has a characteristic of activation function and at least one of the non-linear devices has a characteristic of neuronal function.

Abstract: The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of cross-point devices, and one or more first capacitors operatively connected to the plurality of bit lines. Each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines. The crossbar circuit may further include one or more second capacitors operatively connected to the plurality of word lines. The crossbar circuit may further include a plurality of select lines and/or one or more third capacitors operatively connected to the select lines.

Abstract: The present disclosure provides for transimpedance amplifiers for crossbar circuits. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines and a plurality of cross-point devices. Each of the plurality of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines. The crossbar circuit may further include a transimpedance amplifier to generate an output voltage representative of a sum of currents flowing through a first bit line of the plurality of bit line. The transimpedance amplifier may include an operational amplifier, a current mirror circuit connected to an output of the operational amplifier, and one or more resistors connected to the current mirror circuit and a supply voltage.

Abstract: The present disclosure provides mechanisms for reducing and suppressing random telegraph noise (RTN) for a crossbar circuit. A processing device may perform a programming process to program the conductance of a resistive random-access memory (RRAM) device in the crossbar circuit to a target conductance value. The processing device may then determine whether a random telegraph noise (RTN) value associated with the RRAM device is within a predetermined range of acceptable RTN values. If the RTN value associated with the RRAM device is not within a predetermined range of acceptable RTN values, one or more noise-reduction voltages may be applied to the RRAM device until the RTN value associated with the RRAM device is within the predetermined range of acceptable RTN values.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode; a second electrode comprising an alloy containing tantalum; and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer includes at least one transition metal oxide. The alloy containing tantalum may further contain at least one of hafnium, molybdenum, tungsten, niobium, or zirconium. In some embodiments, the alloy containing tantalum may include one or more of a binary alloy containing tantalum, a ternary alloy containing tantalum, a quaternary alloy containing tantalum, a quinary alloy containing tantalum, a senary alloy containing tantalum, and a high order alloy containing tantalum.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode, a second electrode, and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer comprises at least one transition metal oxide. The second electrode may include a first layer comprising a first metallic material and a second layer comprising a second metallic material. In some embodiments, the first metallic material and the second metallic material may include titanium and tantalum, respectively. In some embodiments, the second electrode may include an alloy of tantalum. The alloy of tantalum may contain one or more of hafnium, molybdenum, niobium, tungsten, and/or zirconium. In some embodiments, the alloy of tantalum contains a plurality of alloys of tantalum.

Abstract: Provided are 3D One-Transistor-N-RRAM (1TNR) structures and One-Selector-One-RRAM (1S1R) structures and methods for manufacturing the same. An example 3D 1TNR structure comprises: a plurality of gate lines; and a plurality of crossbar arrays (e.g., a first crossbar array and a second crossbar array). The first and second crossbar arrays are positioned on a first vertical plane and a second vertical plane, respectively. Each crossbar array in the plurality of crossbar arrays includes a first plurality of bit lines and a second plurality of word lines; Each word line in the second plurality of word lines is connected to a source and a destination of a second transistor; and each gate line in the plurality of gate lines is connected to a gate of a first transistor located in the first crossbar array and a gate of a second transistor located in the second crossbar array.

Abstract: The present disclosure provides an apparatus, including: a substrate; a bottom electrode formed on the substrate; a first base oxide layer formed on the bottom electrode; a first geometric confining layer formed on the first base oxide layer, wherein the first geometric confining layer comprises a first plurality of pin-holes; a second base oxide layer formed on the first geometric confining layer and connected to a first top surface of the first base oxide layer via the first plurality of pin-holes; and a top electrode formed on the second base oxide layer. The first base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof.

Abstract: A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide layer comprising at least one transition metal oxide; a top electrode, and an interface between the switching oxide layer and the top electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x?2.0, and wherein y?2.5. The interface layer comprises a layer of at least one of Al2O3, MgO, Y2O3, or La2O3. The forming-free RRAM device may be switched to multiple resistance levels without a forming process.

Abstract: The present application provides methods for programming a circuit device with reduced disturbances. The methods may include: selecting a first target device on a target row of a plurality of rows and a target column of a plurality of columns; selecting the target row; connecting the plurality of rows other than the target row to a voltage potential with the same polarity as a programming signal; grounding the target column; preparing the programming signal on the target rows; sending a pulse signal enable an access transistor on the target column; and sending the programming signal to pass the first target device.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. An RRAM device may include a first electrode, an interface layer fabricated on the first electrode, a switching oxide layer comprising at least one transition metal oxide; and a second electrode fabricated on the switching oxide layer. The interface layer may include a discontinuous layer of a dielectric material and a conductive material deposited in the discontinuous layer of the dielectric material. The interface layer is positioned between the first electrode and the switching oxide layer. The dielectric material may be and/or include Al2O3, SiO2, Si3N4, MgO, Y2O3, Gb2O3, Sm2O3, CeO2, Er2O3, La2O3, etc. The conductive material may include a metal, a conductive oxide, a conductive nitride, etc.

Abstract: The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.

Abstract: The present disclosure relates to crossbar circuits utilizing resistive random-access memory (RRAM) devices. A crossbar circuit may include a plurality of word lines intersecting with a plurality of bit lines, and a plurality of cross-point devices. Each of the cross-point devices is connected to one of the word lines and one of the bit lines and includes a resistive random-access memory (RRAM) device. The crossbar circuit may further include one or more current digital-to-analog converters (IDACs) configured to perform digital-to-analog conversion. The IDACs are selectively connected to the word lines or the bit lines to provide programming signals to program the RRAM devices to predetermined conductance values. The IDACs may linearly control the compliance currents of the RRAM devices to program the RRAM devices to multiple linearly separated conductance values.

Abstract: Systems and methods for mitigating defects in a crossbar-based computing environment are disclosed. In some implementations, an apparatus comprises: a plurality of row wires; a plurality of column wires connecting between the plurality of row wires; a plurality of non-linear devices formed in each of a plurality of column wires configured to receive an input signal, wherein at least one of the non-linear device has a characteristic of activation function and at least one of the non-linear device has a characteristic of neuronal function.

Abstract: A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide layer comprising at least one transition metal oxide; a top electrode, and an interface between the switching oxide layer and the top electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x?2.0, and wherein y?2.5. The interface layer comprises a layer of at least one of Al2O3, MgO, Y2O3, or La2O3. The forming-free RRAM device may be switched to multiple resistance levels without a forming process.

Abstract: The present disclosure relates to voltage-mode crossbar circuits that may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of cross-point devices, and a plurality of sensing circuits configured to amplify bit line voltages settled on the bit lines in response to an application of input voltages to the cross-point devices via the word lines and generate digital outputs representative of the amplified bit line voltages. Each cross-point device is connected to one of the word lines and one of the bit lines and may include a resistive random-access memory (RRAM) device. Each cross-point device may further be connected to a local select line that may enable a group of cross-point devices connected to one or more bit lines. A cross-point device may be enabled when both a global select line and the local select line connected to the cross-point device are enabled.