Abstract: Technologies relating to CMOS image sensors with integrated Resistive Random-Access Memory (RRAMs) units that provide energy efficient analog storage, ultra-high speed analog storage, and in-memory computing functions are disclosed. An example CMOS image sensor with integrated RRAM crossbar array circuit includes a CMOS image sensor having multiple pixels configured to receive image signals; a column decoder configured to select the pixels in columns to read out; a row decoder configured to select the pixels in rows to read out; an amplifier configured to amplify first signals received from the CMOS image sensor; a multiplexer configured to sequentially or serially read out second signals received from the amplifier; and a first RRAM crossbar array circuit configured to store third signals received from the multiplexer.

Abstract: Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line; a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.

Abstract: Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.

Abstract: Technologies relating to using a slew rate controller to reduce disturbance in a crossbar array circuit are disclosed. An example crossbar array circuit includes: one or more bit lines; one or more word lines; one or more 1T1R cells connected between the bit lines and the word lines; one or more ADCs connected to the one or more bit lines; one or more DACs connected to the one or more word lines; one or more access controls connected to the one or more 1T1R cells and configured to select a 1T1R cell in the one or more 1T1R cells and to program the selected 1T1R cell; and a slew rate controller connected to the DACs, wherein the slew rate controller is configured to receive an input signal. The slew rate controller may be configured to transform a step function input signal into a slew rate input signal.

Abstract: Provided are 3D One-Transistor-N-RRAM (1TNR) structures and One-Selector-One-RRAM (1S1R) structures and methods for manufacturing the same. An example 3D 1TNR structure comprises: a plurality of gate lines; and a plurality of crossbar arrays (e.g., a first crossbar array and a second crossbar array). The first and second crossbar arrays are positioned on a first vertical plane and a second vertical plane, respectively. Each crossbar array in the plurality of crossbar arrays includes a first plurality of bit lines and a second plurality of word lines; Each word line in the second plurality of word lines is connected to a source and a destination of a second transistor; and each gate line in the plurality of gate lines is connected to a gate of a first transistor located in the first crossbar array and a gate of a second transistor located in the second crossbar array.

Abstract: Technologies relating to increasing the surface area of selectors in crossbar array circuits are provided. An example apparatus includes: a substrate; a first line electrode formed on the substrate; an RRAM stack formed on the first line electrode, wherein the RRAM stack; an isolation layer formed beside the RRAM stack, wherein the isolation layer includes an upper surface and a sidewall, and a height from the upper surface to the first line electrode is 100 nanometers to 10 micrometers; a selector stack formed on the RRAM stack, the sidewall, and the upper surface; and a second line electrode formed on the selector stack.

Abstract: An example method includes: forming a bottom electrode on a substrate and forming a patterned mask layer on the bottom electrode; thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma; removing a gaseous status of the bottom electrode oxide using a first vacuum purge; removing a solid status of the bottom electrode oxide by applying a second plasma; removing the gaseous status and the solid status of the bottom electrode oxide using a second vacuum purge to form a patterned bottom electrode; removing the patterned mask layer; forming a filament forming layer on the patterned bottom electrode; and a top electrode on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive to a switching voltage being applied to the filament forming layer.

Abstract: Technologies relating to implementing memristor crossbar arrays using non-filamentary RRAM cells are disclosed. In some implementations, an apparatus comprises: a first row wire; a first column wire; a non-filamentary RRAM; and an access control device. The non-filamentary RRAM and the access control device are serially connected; the non-filamentary RRAM and the access control device connect the first row wire with the first column wire. The non-filamentary RRAM and the access control device may form a cross-point device. The cross-point device may be less than 40×40 nm2. A set current of the non-filamentary RRAM may be no more than 10 ?A; and a reset current of the non-filamentary RRAM is no more than 10 ?A. The access control device may comprise a transistor or a selector.

Abstract: Systems and methods for reducing RRAM relaxation in crossbar array circuits for low current applications are provided. In some implementations, an apparatus comprises: a first row wire; a first column wire; an RRAM device; an access control device, wherein the RRAM device and the access control device serially connected and connecting between the first row wire and the first column wire, and wherein the RRAM device comprises: a first electrode; a first switching layer formed on the first electrode; and a second electrode formed on the first switching layer, wherein the first switching layer is doped with a first oxide material comprising SiO2, or Al2O3. The first electrode and the second electrode are, in some implementations, made of one of the following materials: Pt, Pd, Ta, Ti, Hf, W, TiN, and TaN.

Abstract: Technologies relating to improving LRS data retention and reliability in RRAM-based crossbar array circuits are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; and a top electrode formed on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive a switching voltage being applied to the filament forming layer. The filament forming layer may be made of one of the following materials: HfOxSiy, HfOxNy, HfOxAly, HfOx doped with SiO2, HfOx doped with Al2O3, HfOx doped with N, HfOx doped with Si3N4, HfOx doped with AlN, or a combination thereof. The bottom electrode or the top electrode may be made of one of the following materials: Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, Ru, TaN, NbN, a combination therefore, or an alloy with other electrically conductive materials.

Abstract: Technologies relating to folded crossbar array circuits and methods for reducing pitch match issues within folded crossbar array circuits and increasing the scalability of folded crossbar array circuits are disclosed. An example crossbar array circuit includes: a first folded column circuit folded as at least two portions; a first ADC; a first plurality of DACs; and a first plurality of access controls, wherein the first folded column circuit connected to the first ADC, the first plurality of DACs, and the first plurality of access controls. In some implementations, the three portions comprises a first column of crossbar devices, a second column of crossbar devices, and a third column of crossbar devices, and wherein the first column of crossbar devices, the second column of crossbar devices, and the third column of crossbar devices are configured to be controlled by the first plurality of access controls.

Abstract: The technology of a crossbar array circuit and method of improving thermal shielding are disclosed. An example apparatus includes a bottom wire; a first vertical thermal shielding layer formed on the bottom wire, a bottom electrode formed on the first vertical thermal shielding layer; a filament forming layer formed on the bottom electrode; a top electrode formed on the filament forming layer; a second vertical thermal shielding layer formed on the top electrode; a top wire formed on the second vertical thermal shielding layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the first vertical thermal shielding layer and the second vertical thermal shielding layer includes ReOx, RuOx, IrOx, ITO, a combination thereof, or an alloy or doping thereof (with or without other thermally conductive materials).

Abstract: Technologies relating to one-selector-one-memristor (1S1R) crossbar array circuits methods for reducing 1S1R cell-to-cell switch variations are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; an oxidized filament forming layer; a channel forming layer formed on the filament forming layer; an oxidized filament forming layer; a top electrode formed on the channel forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer, the channel forming layer is configured to form a channel within the channel forming layer when applying a switching voltage upon the filament forming layer and the channel forming layer, and wherein the filament forming layer is surrounded by the oxidized filament forming layer and the channel forming layer is surrounded by the oxidized channel forming layer.

Abstract: Technologies relating to RRAM-based crossbar array circuits with increase temperature stability are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; and a top electrode formed on the filament forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the filament includes nitrogen-doped Ta2O5, Ta2N/Ta2O5, or TaNyOz.

Abstract: Technologies relating to RRAM-based crossbar array circuits and more specifically to reducing row switch resistance error of in crossbar array circuits are disclosed. An example apparatus includes: a first Op-amp including a first inverting Op-amp input, a first non-inverting Op-amp input, and a first Op-amp output; a row switch device including a row switch input and a row switch output; a crossbar array including a row wire, a column wire, and a cross-point device connected between the row wire and the column wire. The row switch input is connected to the first Op-amp output; the row switch output is connected to the first inverting Op-amp input; and the row switch output is connected to the row wire.

Abstract: Systems and methods for mitigating defects in a crossbar-based computing environment are disclosed. In some implementations, an apparatus comprises: a plurality of row wires; a plurality of column wires connecting between the plurality of row wires; a plurality of non-linear devices formed in each of a plurality of column wires configured to receive an input signal, wherein at least one of the non-linear device has a characteristic of activation function and at least one of the non-linear device has a characteristic of neuronal function.

Abstract: Implementing phase change material-based selectors in a crossbar array are disclosed. In some implementations, an apparatus comprises: a plurality of row wires; a plurality of column wires; and a plurality of cross-point devices connecting the plurality of row wires and the plurality of column wires. Each cross-point devices comprises: a memristor device and a selector device formed on the memristor device. The selector device is configured to when in an OFF state, selectively transmit a programming signal to the memristor device; and switch the memristor device to a predefined resistance state when the programming signal includes a voltage pulse higher than a predefined threshold voltage of the selector device and shorter than a crystallization time of the selector device. The selector device is further configured to, when selectively transmitting the programming signal to the memristor device, temporarily switch itself from the OFF state into an ON state.

Abstract: Technologies for reducing series resistance are disclosed. An example method may comprise: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

Abstract: Systems and methods for providing a non-rewritable code comparator using a memristor and a serial resistor are disclosed. An example apparatus comprises: a plurality of first terminals; a plurality of second terminals; and a plurality of two-terminal device pairs formed between the plurality of first terminals and the plurality of second terminals. Each two-terminal device pair in the plurality of two-terminal device pairs include at least one memristor and at least one resistor; each two-terminal device pair is configured to be switched to a subsequent state once and only once. In some implementations, a two-terminal device pair is configured to remain in the subsequent state regardless of whether an input signal to the apparatus matches a reference signal to the apparatus.

Abstract: Code comparators with nonpolar dynamical switches are provided. An example apparatus comprises: a plurality of row wires; a plurality of column wires; one or more cross-point devices, and a nonpolar volatile two-terminal device formed within a plurality of cross-point devices. Each cross-point device in the plurality of cross-point devices is located at a cross-point between a row in the plurality of row wires and a column in the plurality of column wires; the nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device. The nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device.