Abstract: In described examples, an integrated circuit comprises: a substrate; a semiconductor die on the substrate; and a device on the substrate and electrically coupled to the semiconductor die, the device including a polymer structure coated with a metal.

Abstract: A network includes an intermediate node to communicate with a child node via a wireless network protocol. An intermediate node synchronizer in the intermediate node facilitates time synchronization with its parent node and with the child node. A child node synchronizer in the child node to facilitates time synchronization with the intermediate node. The intermediate node synchronizer exchanges synchronization data with the child node synchronizer to enable the child node to be time synchronized to the intermediate node before the intermediate node is synchronized to its parent node if the intermediate node has not synchronized to its parent node within a predetermined guard time period established for the child node.

Abstract: A circuit includes a phase detector configured to produce a first up signal and a first down signal based on a difference between a reference clock and a feedback clock and a harmonic detector coupled to the phase detector, the harmonic detector configured to produce a second up signal based on the first up signal and whether the harmonic detector detects a harmonic lock between the reference clock and the feedback clock based on a first clock phase and a second clock phase. Additionally, the circuit includes a false lock detector coupled to the phase detector and to the harmonic detector, the false lock detector configured to produce a second down signal based on the first down signal and whether the false lock detector detects a false lock between the reference clock and the feedback clock based on a third clock phase and a fourth clock phase.

Abstract: A system includes an LED assembly including a first LED, the first LED configured to produce first light having a first color, a second LED adjacent the first quadrant, the second LED configured to produce second light having a second color, a third LED adjacent the second quadrant, the third LED configured to produce third light having a third color, and a fourth LED adjacent the third quadrant and the first quadrant, the fourth LED configured to produce fourth light having the third color. The system includes a reflective element having a first surface and a second surface, the first surface configured to reflect the first light towards a homogenizing element and to reflect the second light towards the homogenizing element, and the second surface configured to reflect the third light towards the homogenizing element and to reflect the fourth towards the homogenizing element.

Abstract: In described examples, an apparatus comprises a multi-modulus divider (MMD) having a divider input, a divisor input, and a divider output. The apparatus also comprises a phase detector (PD) having a first clock input, a second clock input, and a PD output, the second clock input coupled to the divider output. The apparatus also comprises a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output. The apparatus further comprises a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the divider output, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.

Abstract: A system includes a load and a switching converter coupled to the load. The switching converter includes at least one switching module and an output inductor coupled to a switch node of each switching module. The switching converter also includes a controller coupled to each switching module, where the controller is configured to adjust a pulse clock rate and a switch on-time for each switching module. The controller comprises a pulse truncation circuit configured to detect a voltage overshoot condition and to truncate an active switch on-time pulse in response to the detected voltage overshoot condition.

Abstract: A bidirectional level shifter circuit includes first and second driver circuits, first and second comparators, and a control circuit. The first driver circuit includes a first driver output and a first enable input. The second driver circuit includes a second driver output and a second enable input. The first comparator includes a first comparator output, a first reference input, and a first comparator input that is coupled to the second driver output. The second comparator includes a second comparator output, a second reference input, and a second comparator input is coupled to the first driver output. The control circuit includes a first control input coupled to the first comparator output, a second control input coupled to the second comparator output, a first control output coupled to the first enable input, and a second control output coupled to the second enable input.

Abstract: A compensation circuit comprising: a first source having an output; a second source having an output; a first transistor having a first current terminal coupled to the output of the first source, a second current terminal coupled to ground and a first control terminal connected to the first current terminal; a second transistor having a second control terminal, a third current terminal coupled to the output of the second source and a fourth current terminal coupled to ground; a first resistor connected between the first control terminal and the second control terminal; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor connected to the second control terminal.

Abstract: A multilayer package substrate includes a plurality of dielectric layers including a top dielectric layer on a top side and a bottom dielectric layer on a bottom side. A top patterned metal layer is on the top dielectric layer and a bottom patterned metal layer is on the bottom dielectric layer. At least one of the top dielectric layer and the bottom dielectric layer is a porous dielectric layer having a plurality of pores including an average porosity of at least 5% averaged over its thickness.

Abstract: An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns.

Abstract: A non-transitory computer-readable medium stores instructions executable by a processor to process data from a radar circuit having multiple antennas.

Abstract: The present disclosure generally relates to an electronic device peripheral cleaning cabinet and a method for cleaning such peripherals. In an example, a peripheral cleaning cabinet includes a cabinet body, a door, a cabinet gas line, and a support shelf. The cabinet body includes an exhaust port. The door is mechanically coupled to the cabinet body. The cabinet gas line includes a gas valve and a nozzle. The gas valve is fluidly coupled to the nozzle. The nozzle is disposed in the cabinet body. The cabinet gas line is configured to supply a gas to flow into the cabinet body. The support shelf is disposed in the cabinet body and is configured to support a peripheral. The support shelf is configured to allow the gas to flow from the nozzle, through the support shelf, and to the exhaust port.

Abstract: Ultrasonic audio processing circuitry and a method useful in ultrasonic presence detection. An ultrasonic burst generator produces an ultrasonic burst signal at one or more ultrasonic frequencies, and an equalizer equalizes that ultrasonic burst signal according to frequency response characteristics of the speaker and microphone at those ultrasonic frequencies. Driver circuitry drives a speaker with the ultrasonic burst signal, which may be combined with an audible audio signal. An ultrasonic separation filter separates an ultrasonic portion from a signal received at a microphone, and processing circuitry is provided to determine a delay time of an echo corresponding to the ultrasonic burst signal in that separated ultrasonic portion of the received signal. In another aspect, the equalizer equalizes an ultrasonic portion of the signal received at a microphone, according to frequency response characteristics of the speaker and microphone at the ultrasonic frequencies of the burst.

Abstract: A method of forming an integrated circuit, including first, positioning a semiconductor wafer in a processing chamber; second, exposing portions of the semiconductor wafer, including introducing a first amount of hydrogen into the processing chamber and introducing a first amount of oxygen into the processing chamber; and, third, introducing at least one of a second amount of hydrogen or a second amount of oxygen into the processing chamber, the second amount of hydrogen greater than zero and less than the first amount of hydrogen and the second amount of oxygen greater than zero and less than the first amount of oxygen.

Abstract: Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

Abstract: In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.

Abstract: An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.

Abstract: In described examples, a method of routing messages in a system on a chip (SoC) includes a secure message router receiving a message including a content, an identifier of the message's sending (origin) functional block and/or of a receiving (destination) functional block, a message secure value, a promote value, and a demote value. A context corresponding to the identifier is retrieved from a memory. The context includes an allow promote value and an allow demote value. The message secure value is increased if the promote value requests the increase and matches the allow promote value. The message secure value is decreased if the demote value requests the decrease and matches the allow demote value. Cleartext corresponding to the content is made accessible by the destination if the context secure value matches the message secure value. The message is then outputted from the secure message router to the destination.

Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.