Abstract: A vehicular battery management system (BMS) comprises a battery controller, a set of battery cells, a primary network node coupled to the battery controller, and a secondary network node coupled to the set of battery cells. The primary and secondary network nodes are configured to wirelessly communicate with each other using frames that share a common frame format. The frame format includes one or more bits and a status of the one or more bits indicates whether the secondary network node is to communicate with the primary network node on behalf of another secondary network node.

Abstract: Authentication of a networked device with limited computational resources for secure communications over a network. Authentication of the device begins with the supplicant node transmitting a signed digital certificate with its authentication credentials to a proxy node. Upon verifying the certificate, the proxy node then authenticates the supplicant's credentials with an authentication server accessible over the network, acting as a proxy for the supplicant node. Typically, this verification includes decryption according to a public/private key scheme. Upon successful authentication, the authentication server creates a session key for the supplicant node and communicates it to the proxy node. The proxy node encrypts the session key with a symmetric key, and transmits the encrypted session key to the supplicant node which, after decryption, uses the session key for secure communications. In some embodiments, the authentication server encrypts the session key with the symmetric key.

Abstract: Embodiments include methods of powerline communications using a preamble with band extension is provided. A method may include receiving a packet data unit PDU. Bit-level repetition is applied to at least a portion of the PDU to create a repeated portion. Interleaving is performed per a subchannel. Pilot tones are inserted in the interleaved portion. Each data tone is modulated with respect to a nearest one of the inserted pilot tones. The PDU is transmitted over a power line.

Abstract: An integrated circuit (IC) package comprises a semiconductor die having a first surface with a Hall-effect sensor circuit and a second surface. A plurality of through substrate vias (TSV) each having a metal layer extend from the first surface of the semiconductor die to the second surface. The IC package includes a portion of a leadframe having a first set of leads and a second set of leads. The first set of leads provide a field generating current path for directing a magnetic field toward the Hall-effect sensor circuit. The second set of leads are attached to bond pads on the semiconductor die. A first side of an insulator is attached to the leadframe using a die attach material, and a second side of the insulator is attached to the first side of the semiconductor die using a bonding material.

Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

Abstract: In a circuit for DC-DC voltage converters, an amplifier has first and second inputs coupled to a reference voltage terminal and an output voltage terminal, respectively. A comparator has first and second inputs coupled to an amplifier output and a switching terminal, respectively. A logic circuit has inputs coupled to the comparator output and a clock terminal. A driver circuit has first and second inputs coupled to first and second logic outputs, respectively. A first transistor having a first control terminal coupled to the first driver output is coupled between a supply voltage terminal and the switching terminal. A second transistor is coupled between the switching terminal and a ground terminal, and has a second control terminal coupled to the second driver output. A threshold detection circuit is configured to provide a threshold signal responsive to a current through the second transistor crossing a current threshold.

Abstract: A switch-mode power supply and a zero current detector for use therein. A zero current detector includes an input stage and an output stage. The output stage is coupled to the input stage. The output stage includes a detector output terminal, a first transistor, and a second transistor. The first transistor includes an input terminal and a control terminal. The input terminal is coupled to the detector output terminal. The control terminal is coupled to the input stage. The second transistor includes an input terminal, a control terminal, and an output terminal. The input terminal is coupled to the control terminal of the first transistor. The control terminal is coupled to the input terminal of the second transistor. The output terminal is coupled to ground.

Abstract: Address resolution information acquisition (ARIA) for a computing device is described. In some examples, ARIA includes a computing device (e.g., an Internet of things (IoT) node, a gateway, a server) determining, without use of an address resolution protocol (ARP), address resolution information of one or more other computing devices (e.g., a IoT node, a gateway, a server). In one example, the computing device uses data flowing to or from its application layer, transport layer, or network layer to determine address resolution information of another computing device. The address resolution information can comprise one or more of a link layer address (e.g., a media access control (MAC) address) and an Internet layer address (e.g., an Internet protocol (IP) address). Usage of a cache for storing or deleting address resolution information can also be part of ARIA.

Abstract: A method includes determining by a primary node a network formation process to establish a network with a secondary node according to a network condition of the primary node and the secondary node, the secondary node previously paired to the primary node in a previously established network connection between the primary node and the secondary node, performing by the primary node a scanning phase as part of the network formation process with the secondary node according to network configuration information stored by the primary node and the secondary node and obtained by the primary node and the secondary node in the previously established network connection; and skipping by the primary node a pairing phase of the network formation process with the secondary node responsive to the secondary node being previously paired to the primary node in the previously established network connection.

Abstract: In at least one example, an apparatus includes a current sense circuit, an imbalance detector, and a current balancer. The current sense circuit including a first phase input, a second phase input, a first sense output, and a second sense output. The imbalance detector having a detector output, a first detector input, and second detector input. The first detector input is coupled to the first sense output and the second detector input is coupled to the second sense output. The current balancer having a balancer input and a balancer output. The balancer input is coupled to the detector output.

Abstract: A technique for power aware event scheduling including receiving, from a wireless access point, an indication of a scheduled reference event, determining, for an application event, an amount of time to generate data for a wireless uplink transmission associated with the application event, receiving timing information, the timing information indicating an amount of time to divide the generated data into data frames, determining an adjusted time based on the amount of time to generate data, the received timing information, and the scheduled reference event, triggering the application event at the adjusted time, and transmitting the data frames based on the scheduled reference event.

Abstract: An integrated circuit device (100) and method comprising an IC chip (102) having metal interconnect levels (M1-Mn) including a last copper interconnect level (Mn) and a chip-to-package interconnect (110) overlying and connected to the last copper interconnect level (Mn). The chip-to-package interconnect (110) having a via (112) connected to a first element (306a) of the last copper interconnect level (Mn) and a copper conductive structure (118) (e.g., bump copper). The via (112) includes a barrier material (112a) and a tungsten fill layer (112b), the via coupled between the copper conductive structure (118) and the first element (306a).

Abstract: A system including at least one processor configured to determine a command pattern and a projector coupled to the at least one processor. The projector is configured to project an opening pattern, project the command pattern after projecting the opening pattern, and project a closing pattern after projecting the command pattern.

Abstract: In an example, a method includes depositing an organic polymer layer on one or more material layers. The method also includes thermally curing the organic polymer layer. The method includes depositing a hard mask on the organic polymer layer and depositing a photoresist layer on the hard mask. The method also includes patterning the photoresist layer to expose at least a portion of the hard mask. The method includes etching the exposed portion of the hard mask to expose at least a portion of the organic polymer layer. The method also includes etching the exposed portion of the organic polymer layer to expose at least a portion of the one or more material layers.

Abstract: A calibration circuit providing a programmable voltage generator that is selectively connectable to a first capacitor plate of a capacitive structure to supply a voltage thereto. A reference voltage generator is coupled to the output of the programmable voltage generator and generates a reference voltage. A comparator receives the reference voltage and a discharging voltage from the capacitive structure during a discharge period and, based on those inputs, generates a signal that is output to a digital controller. A constant current source is selectively connectable to the capacitive structure to generate a constant current. Based on the output of the comparator, the constant current, and a count representing a time during which the discharging voltage decreases, the digital controller measures capacitance to calibrate a movable mirror of the capacitive structure. During calibration, the digital controller controls the programmable voltage generator and a second capacitor plate of the capacitive structure.

Abstract: An algorithm for the promotion of terminal nodes to switch nodes in a PLC network reduces overall network overhead and collisions, while ensuring the appropriate selection of a switch node and minimizing the number of levels in a PLC network. It also ensures that the terminal nodes with appropriate signal-to-noise ratios (SNRs) are promoted. It is desirable to have a network with fewer levels. The disclosed approach favors the nodes that are closer to the DC to promote them as switch nodes. This is achieved by waiting for a smaller number of PNPDUs for a node that is closer to the DC in comparison to a node that is farther away from the DC.

Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.

Abstract: In examples, a vehicular battery management system (BMS) comprises a set of battery cells and a secondary network node coupled to the set of battery cells. The secondary network node is configured to measure a parameter in the set of battery cells and generate a packet containing the parameter. The packet indicates a number of super frame slots that have elapsed from a start time of a super frame to the generation of the packet. The secondary network node is configured to wirelessly transmit the packet within the super frame to a primary network node. The primary network node is configured to wirelessly receive the packet and to determine a time at which the secondary network node generated the packet based on the indication, a time duration of each slot in the super frame, and the start time of the super frame.