Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: An electronic device is provided which comprises a microprocessor for executing a program code and a first hardware code path verifying (CPV) stage coupled to the microprocessor. The hardware CPV stage comprises a first error detection code (EDC) generator configured to continuously determine an error detection code on a continuous sequence of code relating to an actually executed portion of the program code and to compare the actual error detection code with a predetermined error code so as to verify correct execution of the program code and to indicate an error.

Abstract: An adaptive slope generator can include a current mirror configured to receive a multiplied current that varies as a function of an output voltage and a switching frequency of a switching current. The output voltage can characterize the switching current provided to a load coupled to an inductor. The current mirror can also be configured to receive an oscillation current. The oscillation current can have an amplitude that corresponds to the switching frequency of the switching current. The current mirror can be further configured to generate an output current substantially equivalent to the product of the oscillation current and the output voltage. The adaptive slope generator can also include a ramp generator configured to generate a compensation signal based on the output current. The compensation signal can have a sawtooth shape and a slope that varies as a function of the output voltage.

Abstract: An electronic device, including a first limiter including a first transistor configured to be coupled with a first side of a channel to a first output node of a non-ideal voltage source having an inner impedance greater zero in order to limit the voltage at the first output node by drawing a current from the first output node. The second side of the channel of the first transistor is coupled to a capacitor so as to supply a current from the first output node to the capacitor, if the voltage level at the output node reaches or exceeds an upper limit.

Abstract: An electronic device is provided that is adapted to generate a supply voltage at an input node from a radio frequency (RF) signal. The electronic device includes a limiter coupled to the input node for limiting a supply voltage level at the input node that is generated by the received RF signal. The limiter is configured to draw a limiter current from the input node so as to limit the supply voltage level to a maximum and a magnitude of the limiter current is used for controlling a power consumption of the electronic device.

Abstract: A DC-DC converter has a control circuit for controlling a high-side power transistor and a low-side power transistor connected in series between supply terminals to which an input supply voltage is applied. The converter has a switching node at the interconnection of the power transistors for connection of an inductor to which a load is connected. The control circuit has a feedback loop that provides a pulse width modulated control signal, logic circuitry to which the pulse width modulated control signal is applied and gate drivers with inputs connected to outputs of the logic circuitry and outputs applying gate drive signals to the gates of the power transistors. A digital signal is obtained which is indicative of whether the converter switching node is at a potential above or below a zero reference at the time of the turn-off edge of the low-side gate drive signal.

Abstract: Self-monitoring reset circuitry is presented for use in analog-to-digital converters and other modulator circuitry with capacitively coupled isolation barriers in which the modulator output data is monitored for inactivity by a reset circuit synchronized to the modulator clock, and extra pulses are selectively introduced into the data prior to transmission across the isolation barrier if no modulator state changes occur within a predetermined number of clock cycles to provide a predictable data output value for each end of the analog input range and to reset the output to the correct state in situations where transient noise toggles the output and the modulator output is static.

Abstract: Embodiments of the invention relate to automatic test equipment for testing a circuit having an oscillating crystal and to a method for operating such automatic test equipment. A generator generates a first signal comprising an oscillating part having at least one predetermined frequency. A first terminal couples the first signal to the oscillating crystal. At least one predetermined frequency is located inside a predetermined window around one of the resonance frequencies of the oscillating crystal. An analyzer has a second terminal coupled to the oscillating crystal for detecting a second signal and a rectifier connected in series with a low-pass filter for rectifying and filtering the second signal. A detector for detects a DC-signal at the output of the low-pass filter and for signals a valid test result for the oscillating crystal if the DC-signal exceeds a certain threshold value.

Abstract: The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.

Abstract: An electronic device for DC-DC conversion including a feedback loop coupled at one side to the inductor for measuring a current through the inductor with a series of an auxiliary capacitor and an auxiliary resistor, a transconductance stage coupled to the auxiliary capacitor for generating a current proportional to a voltage drop across the auxiliary capacitor, wherein the electronic device further includes a ramp resistor coupled to the output of the transconductance stage for generating a ramp voltage across the ramp resistor and a comparator receiving at a first input the ramp voltage, wherein the output of the comparator is coupled to a gate driving stage for driving a power transistor coupled with a control gate to the gate driving stage and with a channel to a switching node of the electronic device.

Abstract: Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second transimpedance amplifiers with input transistors operating according to bias currents from a biasing circuit, output transistors and adjustable feedback impedances modified using an automatic gain control circuit, as well as a reference circuit controlling the bias currents according to an on-board reference current and the single-ended input or the differential output voltage signals from the transimpedance amplifiers.

Abstract: A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other.

Abstract: A voltage regulator for providing power to a system includes feedforward circuitry receiving a signal from the system indicating the current needed by the system, and the feedforward circuitry causes the voltage regulator to change the voltage regulator output current in response to the signal from the system.

Abstract: A first sensor detects whether an object is within a first region that surrounds the first sensor. A second sensor detects whether the object is within a second region that surrounds the second sensor. The first and second sensors are omnidirectional capacitive electrodes. In response to the first sensor detecting that the object is not within the first region, a device determines that the object is not proximate to a particular side of the first and second sensors. In response to the first sensor detecting that the object is within the first region, and the second sensor detecting that the object is within the second region, the device determines that the object is not proximate to the particular side. In response to the first sensor detecting that the object is within the first region, yet the second sensor detecting that the object is not within the second region, the device determines that the object is proximate to the particular side.

Abstract: An electronic device, a fiber-optic communication system comprising the electronic device and a method of operating the electronic device are provided. The electronic device comprises a transimpedance-type amplifier having a transimpedance stage comprising an amplifier which is coupled in series with an input node. A feedback resistor is coupled in series between an output node of the amplifier and an inverting input node of the amplifier to provide a virtual ground node which is coupled to the input node, the inverting input node of the amplifier and to the feedback resistor. A current source is coupled to the virtual ground node so as to compensate for an offset current in an input signal which is coupled to the input node of the electronic device. Further, the electronic device comprises a control stage which is configured to control the current source as a function of a current through the feedback transistor.

Abstract: An electronic device for a lighting system, comprising a TRIAC dimmer configured to receive a mains supply voltage and provide a phase cut voltage to the electronic device and having a control loop configured to control a duty cycle of a switched voltage converter that receives the rectified input voltage and provides drive current to a light emitting semiconductor device. The control loop has an error amplifier that is coupled to receive a sense voltage that is indicative of a current through the light emitting semiconductor device, the error amplifier is configured to provide a feedback signal to a pulse width modulation logic configured to control the duty cycle of the switched voltage converter to provide a constant drive current to the light emitting semiconductor device in response to the sense voltage, the error amplifier being coupled to receive a reference voltage that is a function of the input voltage.

Abstract: An average current mode buck-boost DC to DC converter has a buck stage coupled between an input voltage source terminal and an output terminal. A boost stage is coupled between the input voltage source terminal and the output terminal. A current ramp control circuit generates a ramp signal for driving the buck and boost stages, the ramp signals being coupled to the buck and boost stages. A constant voltage related to the desired output voltage by a constant is applied directly to both a voltage control feedback loop for adjusting the output voltage and directly to an input to the current ramp control circuit, whereby the output voltage can be shifted from one voltage to another by feedforward control.

Abstract: Electronic device comprising an electronic circuit and an ESD protection circuit is provided. The ESD protection circuit comprises a first and a second protection stage, wherein the second protection stage comprises at least one high side CMOS-transistor and a low side CMOS-transistor acting as power dissipating rail clamps. The at least one high side CMOS-transistor and the low side CMOS-transistor are coupled so as to provide an anti-series connection of Zener diodes between a node of the electronic device and a supply voltage rail. Further, the high side CMOS-transistors and the low side CMOS-transistor are complementary CMOS-transistors.

Abstract: The invention relates to an electronic device and a method for DC-DC-conversion. The electronic device includes energizing switch and a commutating switch coupled at a switching node. The switching node is configured to be coupled to an inductor. The electronic device is configured to repeatedly suspend the regular synchronous switching of the commutating switch during a load detection period, to sense the voltage at the output node during the load detection period and to determine a high-load condition or a light-load condition of the DC-DC-conversion based on the sensed voltage at the output node.

Abstract: A DC-DC converter includes a current control stage configured to provide a threshold based on an output voltage, an input voltage, and a reference voltage for the DC-DC converter. An off time control can be configured to receive the threshold and control an off time for the DC-DC converter based on the threshold such that the off time is inversely proportional to the peak current generated by the DC-DC converter.