Abstract: An integrated CMOS clock generator with a self-biased phase locked loop circuit comprises a phase-frequency detector with a reference signal input, a feedback signal input and an output. A first charge pump of the clock generator has an input connected to the output of the phase-frequency detector and an output that supplies a control voltage. A loop capacitor is connected to the output of the first charge pump. The clock generator further has a second charge pump with an input connected to the output of the phase-frequency detector and an output. In particular, the clock generator has two oscillator blocks.

Abstract: An electronic device includes a DC-DC converter for voltage conversion in a slave mode an in a master mode and including a phase locked loop. The phase locked loop comprises a controlled oscillator, a filter having an integration capacitor coupled to a control input of the controlled oscillator, a charge pump, and a phase frequency detector. In the slave mode, the controlled oscillator, the filter, the charge pump and the phase frequency detector are coupled to operate as the phase locked loop. There is a comparator coupled with an input to a control input of the controlled oscillator and with an output to the charge pump. In the master mode, the comparator is configured to control the charge pump in response to a control signal at the control input of the controlled oscillator when the phase frequency detector is switched off so as to perform a modulation of the control signal at the control input of the controlled oscillator by charging and discharging the integration capacitor.

Abstract: Gamma curve correction circuitry includes first (24-1,2 . . . 11) and second (24-12,13 . . . 22) groups of gamma correction buffers and corresponding DACs (28-1,2 . . . 22). Each buffer has an input coupled to an output of a corresponding DAC, respectively, and an output coupled by a corresponding output conductor, respectively, to a corresponding resistor string tap point. A midrange voltage (V30) is produced with a value approximately midway between a first voltage (VDD) and a second voltage (GND) and is coupled to provide power to the first and second groups of buffers. The first voltage is coupled to a first voltage terminal of a first buffer (24-11) of the first group. A second voltage terminal of the first buffer is coupled to the midrange voltage. The midrange voltage is coupled to a first voltage terminal of a first buffer (24-12) of the second group. A second voltage terminal of the first buffer of the second group is coupled to the second voltage.

Abstract: An average current mode buck-boost DC to DC converter has a buck stage coupled between an input voltage source terminal and an output terminal. A boost stage is coupled between the input voltage source terminal and the output terminal. A current ramp control circuit generates a ramp signal for driving the buck and boost stages, the ramp signals being coupled to the buck and boost stages. A constant voltage related to the desired output voltage by a constant is applied directly to both a voltage control feedback loop for adjusting the output voltage and directly to an input to the current ramp control circuit, whereby the output voltage can be shifted from one voltage to another by feedforward control.

Abstract: A RFID transponder includes a resonant circuit for providing a clock signal at a predetermined clock frequency, a self-calibration stage for calibrating the resonant circuit's current clock frequency towards the predetermined clock frequency. The self-calibration stage is adapted to compare a first clock frequency of the resonant circuit determined during an interrogation period, during which the resonant circuit is excited by an external RF signal, with a second clock frequency determined during a frequency maintenance period, during which the resonant circuit is excited internally through an oscillation maintenance circuit of the RFID transponder and to calibrate the resonant circuit towards the predetermined clock frequency based on the comparison result.

Abstract: A low power DC-DC converter includes a converter stage coupled to an input node, and having a low side switch and a rectifier switch. A peak current detector senses a current at the low side switch and a zero current detector senses a current at the rectifier switch. It is configured to set the low side switch to a non-conductive state and the rectifier switch to a conductive state if the peak current detector detects a predetermined peak current. It is configured to set the rectifier switch to a non-conductive state if the zero current detector detects zero current at the rectifier switch. A time interval between subsequent current peaks is triggered by a charge comparator receiving an average current fed to the low side and rectifier switches from the input node and a reference current coupled to the charge comparator by a reference current source.

Abstract: The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme.

Abstract: The modulator comprises a first and second integration stages, and a comparator, the first integration stage is fully differential having: an amplifier, sets of input sampling capacitors and feedback capacitors, and the first integration stage is configured to sample the analog input voltage on a set of input capacitors during a first portion of a clock cycle and on a set of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a set of feedback capacitors during the first portion of the clock cycle and on a set of feedback capacitors during the second portion of the clock cycle, and the first set of feedback capacitors and the second set of feedback capacitors are randomly selected out of the plurality of sets of feedback capacitors from cycle to cycle.

Abstract: An electronic device comprising an amplifier having at least a first input transistor of a first doping type. A first transistor is coupled with a channel as a feedback path between an output of the amplifier and a control gate of the first input transistor forming an input of the amplifier. A diode-coupled second transistor is coupled with a channel between a first current source and the output of the amplifier wherein a control gate of the first transistor is coupled between the first current source and the diode-coupled second transistor and the first transistor is of a second doping type which is opposite to the first doping type of the first input transistor of the amplifier.

Abstract: An integrated battery charger protection circuit incorporates a charge control power FET for series connection in the battery load current path from a DC supply input terminal to a controlled DC output terminal. The circuit has a gate drive input terminal connected to the gate of the charge control power FET and further includes protective circuitry adapted to disable the DC output terminal in a fault condition detected within the integrated circuit. The controlled DC output terminal and the gate drive input terminal are connectable to the external charge control host circuit the same way as corresponding terminals of a discrete power FET, in particular of p-channel type.

Abstract: The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.

Abstract: An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I2C) or I2C compatible bus. The IC is further configured to receive an address through the I2C bus and store the received address in a register, so as to be identified by the address. A method of address assignment in a master/slave system, the system comprises at least one master, a plurality of slaves, and an I2C or I2C compatible bus. The method comprises sending a first address by the master on the I2C bus to a first of the plurality of slaves and storing the first address on the first slave to identify the first slave by the first address. The method further comprises sending a second address by the master on the I2C bus to a second of the plurality of slaves and storing the second address on the second slave to identify the second slave by the second address. The steps of sending and storing are repeated until all slaves of the system have stored an address.

Abstract: An electronic device and a method for operating an electronic device, wherein the electronic device comprises a reset stage which is configured to have a power down threshold and a power cycle threshold. The voltage level of the power cycle threshold is lower than the voltage level of the power down threshold. The two threshold levels define a first and second interval for a supply voltage of the electronic device. A first interval is between the power cycle threshold and the power down threshold. A second interval is above the power down threshold. The reset stage is further configured to provide the control signal having a defined first state in the first interval and a defined second state in the second interval. The electronic device is set to a low power reset mode if the control signal is in the first state and the electronic device is enabled to enter an active mode if the control signal is in the second state.

Abstract: A buffer is provided. The buffer includes a buffering stage that receives an enable signal and an input signal and that provides an output signal and a bandgap stage that is coupled to the buffering stage and that is activated and deactivated by the enable signal. In particular, the buffering stage includes a buffering substage that includes a buffering transistor that is coupled to the input stage, wherein the buffering transistor is formed on a substrate, and wherein the buffering transistor has a channel with a doping concentration that is approximately the same as the substrate.

Abstract: Single inductor-multiple output (SIMO) DC-DC converter, having an output node which is coupled to one side of the single inductor to receive a load current. A plurality of output switches which are coupled to the output node for switching the load current from the output node to a plurality of output lines is provided. Each output line has a load capacitor. Further, each output line may comprise a charge pump which is coupled to the output switch and the load capacitor of the output line.

Abstract: Apparatus for inspecting a semiconductor wafer (8) has a plurality of light sensors (2) arranged relative to a light source (1) and wafer inspection platform (4), so that images of different angle views of a surface of the wafer can be received and compared with corresponding images taken of a reference wafer to automatically detect defects based on image comparison. The light sensors (2) may receive superposed images of light (7) reflected directly from the light source (1) off the wafer surface and light (6) indirectly reflected off the wafer surface after first reflecting off a dome (3) with a diffusely reflecting inner surface (5) positioned over the platform (4).

Abstract: An electronic device for DC-DC conversion of an input voltage into an output voltage is provided. The electronic device includes a current mode control loop for controlling a sensed current of the DC-DC conversion by comparing a voltage level indicating a magnitude of the sensed current with a reference voltage level indicating the maximum admissible magnitude of the sensed current. The reference voltage level is dynamically adjusted in response to a change of an input voltage level.

Abstract: An electronic device includes a circuit for measuring a current in an inductor, wherein the current in the inductor is controlled by alternately switching a first power transistor and a second power transistor each having a first electrode, a second electrode and a control gate. The measuring circuit includes a first sense transistor having a first electrode, a second electrode and a control gate, the first sense transistor having the control gate coupled to the control gate of the first power transistor. A second electrode is coupled to the second electrode of the first power transistor. A second sense transistor has a first electrode, a second electrode and a control gate, the second sense transistor having the control gate coupled to the control gate of the second power transistor and having the second electrode coupled to the second electrode of the second power transistor.

Abstract: An electronic device is provided for switched DC-DC conversion of an input voltage level into an output voltage level. The electronic device is configured to control a control gate of a power switch and to prevent a charge of a capacitance of the control gate released during a switching operation from flowing to ground.

Abstract: The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.