Patents Assigned to Texas Instruments Deutschland, GmbH
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Patent number: 8941473Abstract: An electronic device comprising a first node to be coupled to a first antenna, a second node coupled to a second antenna, a third node to be coupled to a third antenna, a first comparator coupled with a first input to the first node and with a second input to a second node, a second comparator coupled with a first input to the first node and with a second input to the third node, a third comparator coupled with a first input to the second node and with a second input to the third node. Each of the first, the second and the third comparators are configured to compare a first current and a second current at the first input and the second input.Type: GrantFiled: November 8, 2011Date of Patent: January 27, 2015Assignee: Texas Instruments Deutschland GmbHInventors: Oliver Nehrig, Dirk Preikszat
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Publication number: 20150016006Abstract: Automated degaussing methods and apparatus are presented for degaussing a magnetic core in close loop fashion, in which a plurality of pulses are applied to a compensation coil magnetically coupled with the core with duration or energy being decreased in succeeding pulse cycles according to a discrete feedback algorithm, and with individual pulse polarities being set according to core magnetization polarity measured subsequent to an immediately preceding pulse.Type: ApplicationFiled: February 10, 2014Publication date: January 15, 2015Applicant: Texas Instruments Deutschland GmbHInventors: Caspar Petrus Laurentius van Vroonhoven, Sudarshan Udayashankar, Gebhard Haug, Mikhail Valeryevich Ivanov
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Patent number: 8932942Abstract: Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.Type: GrantFiled: March 23, 2010Date of Patent: January 13, 2015Assignee: Texas Instruments Deutschland GmbHInventors: Philipp Steinmann, Manfred Schiekofer, Michael Kraus, Thomas Scharnagl, Wolfgang Schwartz
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Patent number: 8928299Abstract: A low power DC-DC converter includes a converter stage coupled to an input node, and having a low side switch and a rectifier switch. A peak current detector senses a current at the low side switch and a zero current detector senses a current at the rectifier switch. It is configured to set the low side switch to a non-conductive state and the rectifier switch to a conductive state if the peak current detector detects a predetermined peak current. It is configured to set the rectifier switch to a non-conductive state if the zero current detector detects zero current at the rectifier switch. A time interval between subsequent current peaks is triggered by a charge comparator receiving an average current fed to the low side and rectifier switches from the input node and a reference current coupled to the charge comparator by a reference current source.Type: GrantFiled: May 25, 2012Date of Patent: January 6, 2015Assignee: Texas Instruments Deutschland GmbHInventors: Markus Matzberger, Konrad Wagensohner, Erich Bayer
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Patent number: 8922267Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.Type: GrantFiled: October 6, 2011Date of Patent: December 30, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Carlo Peschke, Ernst Muellner
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Patent number: 8923791Abstract: An RFID transponder having an analog front end receiver having an attenuator coupled to receive an RF-signal from an antenna and to attenuate the RF-signal, an amplifier having a fixed amplifier gain and being coupled to receive and to amplify the attenuated RF-signal and a control unit coupled to control a gain of the attenuator, wherein the control unit is configured to control the attenuator gain in response to a level of the amplified RF-signal, the control unit is configured to have a plurality of predetermined states causing the attenuator to increase (step-up) or to decrease (step-down), its gain by a predefined step size.Type: GrantFiled: December 8, 2011Date of Patent: December 30, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Ernst Muellner, Carlo Peschke
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Publication number: 20140372729Abstract: A processor includes a processor core. The processor core includes a first execution unit and a second execution unit. The first execution unit is configured to 1) execute a complex instruction that requires multiple instruction cycles to execute; 2) generate a wait signal that when asserted suspends execution of instructions by the second execution unit for at least a portion of the execution of the complex instruction; and 3) maintain information defining parameters of the wait signal generation across interruption of the complex instruction by execution of a different instruction in the first execution unit.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventors: Horst Diewald, Johann Zipperer
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Patent number: 8901974Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.Type: GrantFiled: January 30, 2013Date of Patent: December 2, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Puneet Sareen, Markus Dietl, Ketan Dewan, Edmond F. George
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Patent number: 8892943Abstract: An electronic device is provided which comprises a microprocessor for executing a program code and a first hardware code path verifying (CPV) stage coupled to the microprocessor. The hardware CPV stage comprises a first error detection code (EDC) generator configured to continuously determine an error detection code on a continuous sequence of code relating to an actually executed portion of the program code and to compare the actual error detection code with a predetermined error code so as to verify correct execution of the program code and to indicate an error.Type: GrantFiled: August 6, 2010Date of Patent: November 18, 2014Assignee: Texas Instruments Deutschland GmbHInventor: Arni Ingimundarson
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Patent number: 8890587Abstract: An adaptive slope generator can include a current mirror configured to receive a multiplied current that varies as a function of an output voltage and a switching frequency of a switching current. The output voltage can characterize the switching current provided to a load coupled to an inductor. The current mirror can also be configured to receive an oscillation current. The oscillation current can have an amplitude that corresponds to the switching frequency of the switching current. The current mirror can be further configured to generate an output current substantially equivalent to the product of the oscillation current and the output voltage. The adaptive slope generator can also include a ramp generator configured to generate a compensation signal based on the output current. The compensation signal can have a sawtooth shape and a slope that varies as a function of the output voltage.Type: GrantFiled: February 7, 2013Date of Patent: November 18, 2014Assignee: Texas Instruments Deutschland GmbHInventor: Ferdinand Stettner
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Patent number: 8890497Abstract: An electronic device, including a first limiter including a first transistor configured to be coupled with a first side of a channel to a first output node of a non-ideal voltage source having an inner impedance greater zero in order to limit the voltage at the first output node by drawing a current from the first output node. The second side of the channel of the first transistor is coupled to a capacitor so as to supply a current from the first output node to the capacitor, if the voltage level at the output node reaches or exceeds an upper limit.Type: GrantFiled: March 1, 2012Date of Patent: November 18, 2014Assignee: Texas Instruments Deutschland GmbHInventor: Carlo Peschke
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Patent number: 8884599Abstract: A DC-DC converter has a control circuit for controlling a high-side power transistor and a low-side power transistor connected in series between supply terminals to which an input supply voltage is applied. The converter has a switching node at the interconnection of the power transistors for connection of an inductor to which a load is connected. The control circuit has a feedback loop that provides a pulse width modulated control signal, logic circuitry to which the pulse width modulated control signal is applied and gate drivers with inputs connected to outputs of the logic circuitry and outputs applying gate drive signals to the gates of the power transistors. A digital signal is obtained which is indicative of whether the converter switching node is at a potential above or below a zero reference at the time of the turn-off edge of the low-side gate drive signal.Type: GrantFiled: March 21, 2011Date of Patent: November 11, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Stefan Herzer, Sumeet P. Kulkarni, Jochen Neidhardt
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Patent number: 8886123Abstract: An electronic device is provided that is adapted to generate a supply voltage at an input node from a radio frequency (RF) signal. The electronic device includes a limiter coupled to the input node for limiting a supply voltage level at the input node that is generated by the received RF signal. The limiter is configured to draw a limiter current from the input node so as to limit the supply voltage level to a maximum and a magnitude of the limiter current is used for controlling a power consumption of the electronic device.Type: GrantFiled: March 11, 2010Date of Patent: November 11, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Oliver Nehrig, Carlo Peschke
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Patent number: 8873644Abstract: Self-monitoring reset circuitry is presented for use in analog-to-digital converters and other modulator circuitry with capacitively coupled isolation barriers in which the modulator output data is monitored for inactivity by a reset circuit synchronized to the modulator clock, and extra pulses are selectively introduced into the data prior to transmission across the isolation barrier if no modulator state changes occur within a predetermined number of clock cycles to provide a predictable data output value for each end of the analog input range and to reset the output to the correct state in situations where transient noise toggles the output and the modulator output is static.Type: GrantFiled: July 30, 2013Date of Patent: October 28, 2014Assignees: Texas Instruments Deutschland GmbH, Texas Instruments IncorporatedInventors: James Lee Todsen, Caspar Petrus Laurentius van Vroonhoven
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Patent number: 8872523Abstract: Embodiments of the invention relate to automatic test equipment for testing a circuit having an oscillating crystal and to a method for operating such automatic test equipment. A generator generates a first signal comprising an oscillating part having at least one predetermined frequency. A first terminal couples the first signal to the oscillating crystal. At least one predetermined frequency is located inside a predetermined window around one of the resonance frequencies of the oscillating crystal. An analyzer has a second terminal coupled to the oscillating crystal for detecting a second signal and a rectifier connected in series with a low-pass filter for rectifying and filtering the second signal. A detector for detects a DC-signal at the output of the low-pass filter and for signals a valid test result for the oscillating crystal if the DC-signal exceeds a certain threshold value.Type: GrantFiled: November 4, 2011Date of Patent: October 28, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Ralf Sonnhueter, Anton Ecker
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Patent number: 8871603Abstract: The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.Type: GrantFiled: May 3, 2012Date of Patent: October 28, 2014Assignees: Texas Instruments Deutschland GmbH, Texas Instruments IncorporatedInventors: Christoph Andreas Othmar Dirnecker, Leif Christian Olsen
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Patent number: 8866450Abstract: An electronic device for DC-DC conversion including a feedback loop coupled at one side to the inductor for measuring a current through the inductor with a series of an auxiliary capacitor and an auxiliary resistor, a transconductance stage coupled to the auxiliary capacitor for generating a current proportional to a voltage drop across the auxiliary capacitor, wherein the electronic device further includes a ramp resistor coupled to the output of the transconductance stage for generating a ramp voltage across the ramp resistor and a comparator receiving at a first input the ramp voltage, wherein the output of the comparator is coupled to a gate driving stage for driving a power transistor coupled with a control gate to the gate driving stage and with a channel to a switching node of the electronic device.Type: GrantFiled: October 11, 2011Date of Patent: October 21, 2014Assignee: Texas Instruments Deutschland GmbHInventor: Joerg Kirchner
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Publication number: 20140306760Abstract: Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second transimpedance amplifiers with input transistors operating according to bias currents from a biasing circuit, output transistors and adjustable feedback impedances modified using an automatic gain control circuit, as well as a reference circuit controlling the bias currents according to an on-board reference current and the single-ended input or the differential output voltage signals from the transimpedance amplifiers.Type: ApplicationFiled: April 16, 2013Publication date: October 16, 2014Applicant: Texas Instruments Deutschland GmbHInventors: Oliver Piepenstock, Gerd Schuppener, Frank Gelhausen, Ulrich Schacht
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Patent number: 8853094Abstract: A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other.Type: GrantFiled: February 21, 2012Date of Patent: October 7, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Thomas Scharnagl, Berthold Staufer
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Publication number: 20140292293Abstract: A voltage regulator for providing power to a system includes feedforward circuitry receiving a signal from the system indicating the current needed by the system, and the feedforward circuitry causes the voltage regulator to change the voltage regulator output current in response to the signal from the system.Type: ApplicationFiled: April 15, 2013Publication date: October 2, 2014Applicant: Texas Instruments Deutschland GMBHInventors: Florian Feckl, Nigel Peter Smith, Erich Johann Bayer
