Patents Assigned to Texas Instruments Inc.
  • Publication number: 20150244363
    Abstract: A circuit for receiving digital signals over a transmission line. A feedback circuit is coupled to an input node of the transmission line and adjusts the input impedance of the receiver circuit to match the characteristic impedance of the transmission line. The feedback circuit includes a first current source controlled by a first voltage and having a first transconductance, and a second current source controlled by the first voltage and having a second transconductance equal to the first transconductance times a first scaling factor. The feedback circuit includes a first resistance element having a resistance equal to the first scaling factor plus one, times the characteristic impedance of the transmission line, and is coupled between the outputs of the first and second current sources.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Applicant: Texas Instruments, Inc.
    Inventor: Horia GIUROIU
  • Patent number: 9070768
    Abstract: A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: June 30, 2015
    Assignees: X-FAB Semiconductor Foundries AG, Texas Instruments Inc
    Inventors: Ralf Lerner, Phil Hower, Gabriel Kittler, Klaus Schottmann
  • Publication number: 20150030058
    Abstract: The present disclosure provides a receiver, a transmitter and methods of operating a receiver and a transmitter. In one embodiment, the receiver includes a receive portion employing transmission signals from a transmitter, having multiple transmit antennas, that is capable of transmitting at least one spatial codeword and adapting a transmission rank. The receiver also includes a feedback generator portion configured to provide a channel quality indicator that is feedback to the transmitter, wherein the channel quality indicator corresponds to at least one transmission rank.
    Type: Application
    Filed: June 6, 2007
    Publication date: January 29, 2015
    Applicant: Texas Instruments Inc.
    Inventors: Badri Varadarajan, Eko N. Onggosanusi
  • Patent number: 8816669
    Abstract: Various apparatuses and methods for supplying an electrical current are disclosed herein. For example, some embodiments provide an apparatus including a current regulation switch connected in a current path between a power input and a current output. A current regulator is connected to the current regulation switch. The current regulator includes a current set terminal, and the current through the current regulation switch is proportional to the current through current set terminal. An impedance monitor is connected to the current set terminal.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: August 26, 2014
    Assignee: Texas Instruments Inc.
    Inventors: Stephen Christopher Terry, Paul L. Brohlin
  • Publication number: 20130327792
    Abstract: The present invention relates to apparatus and method for re-circulating high viscosity liquids. The apparatus comprises a recirculating probe coupled to a fluid storage and dispensing vessel by a connector, and the recirculating probe comprises: (a) a dip tube defining an output flow path; (b) an output port; (c) a recirculating port; and (d) a return flow path. The output flow path and the return flow path preferably have substantially equal cross-sectional areas, which reduce or eliminate the unbalance between the discharge pressure in the output line and that in the re-circulation line, and prevent premature wearing-out of the dispensing/recirculating pump.
    Type: Application
    Filed: July 29, 2013
    Publication date: December 12, 2013
    Applicants: Texas Instruments Inc., Advanced Technology Materials Inc.
    Inventors: Ryan Priebe, Kevin T. O'Dougherty, Nicholas Cheesebrow
  • Patent number: 8470400
    Abstract: Processes for synthesizing graphene films. Graphene films may be synthesized by heating a metal or a dielectric on a substrate to a temperature between 400° C. and 1,400° C. The metal or dielectric is exposed to an organic compound thereby growing graphene from the organic compound on the metal or dielectric. The metal or dielectric is later cooled to room temperature. As a result of the above process, standalone graphene films may be synthesized with properties equivalent to exfoliated graphene from natural graphite that is scalable to size far greater than that available on silicon carbide, single crystal silicon substrates or from natural graphite.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: June 25, 2013
    Assignees: Board of Regents, The University of Texas System, Texas Instruments, Inc.
    Inventors: Luigi Colombo, Xuesong Li, Rodney S. Ruoff
  • Patent number: 8309438
    Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: November 13, 2012
    Assignees: Board of Regents, The University of Texas System, Texas Instruments, Inc.
    Inventors: Luigi Colombo, Robert M. Wallace, Rodney S. Ruoff
  • Patent number: 8068379
    Abstract: A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select line arranged in parallel to the main word line is extended to a plurality of sub arrays arranged in the extension direction of the word line. A second sub word select line is connected to the corresponding one of said first sub word select line to be extended orthogonally to a word line driving circuit area of an adjacent sub array. In the sub word line driving circuit provided for each sub array, a sub word line is selected and deselected by signals supplied from said main word line and said second sub word select line.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: November 29, 2011
    Assignees: Hitachi, Ltd., Texas Instruments Inc.
    Inventors: Tsutomu Takahashi, Kouji Arai, Yasushi Takahashi, Atsuya Tanaka, Shunichi Sukegawa, Shinji Bessho, Masayuki Hira
  • Publication number: 20110129979
    Abstract: In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition process wherein a temperature of a bottom region of a furnace is higher than a temperature of in the top region and is maintained for a predetermined period. The pre-deposition temperature is changed to a deposition temperature, wherein a temperature of the bottom region is lower than a temperature of the top region.
    Type: Application
    Filed: August 1, 2007
    Publication date: June 2, 2011
    Applicant: Texas Instruments Inc.
    Inventors: Bradley D. Sucher, Christopher S. Whitesell, Joshua J. Hubregsen, James H. Beatty
  • Publication number: 20110090725
    Abstract: Systems and methods for synchronous rectifier control are provided. A synchronous rectifier includes parasitic drain inductance and parasitic source inductance. Compensation inductance is introduced to offset the effects of parasitic inductance. Compensation inductance may be formed from the trace inductance on the semiconductor die. In certain semiconductor packages, the parasitic inductance may be substantially fixed such that the layout can be modified to generate fixed compensation inductance.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 21, 2011
    Applicant: Texas Instruments Inc
    Inventor: Bing Lu
  • Publication number: 20100224851
    Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.
    Type: Application
    Filed: February 16, 2010
    Publication date: September 9, 2010
    Applicants: Board of Regents, The University of Texas System, Texas Instruments, Inc.
    Inventors: Luigi Colombo, Robert M. Wallace, Rodney S. Ruoff
  • Publication number: 20100181655
    Abstract: A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 22, 2010
    Applicants: Board of Regents, The University of Texas System, Texas Instruments, Inc.
    Inventors: Luigi Colombo, Sanjay Banerjee, Seyoung Kim, Emanuel Tutuc
  • Publication number: 20100161256
    Abstract: A circuit and method of determining the power output for a converter circuit includes determining a time averaged voltage from a rectified voltage of a winding of the transformer and multiplying the time averaged voltage by a constant determined at least in part by an average current of a winding of the transformer. By one approach, a rectified voltage from a primary side of the transformer is time averaged using a filter circuit. The current can be known or preset or controlled by the converter circuit such that the time averaged voltage reading, assuming a constant current, can be compared to a preset voltage such that the voltage reading approximates a power reading for the transformer. By another approach, the time averaged voltage is multiplied by the current to obtain a power output reading.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 24, 2010
    Applicant: Texas Instruments, Inc.
    Inventor: Gary David Guenther
  • Publication number: 20100158166
    Abstract: A signal processing circuit is configured to calculate a gain ratio to efficiently reduce a peak to average signal ratio for an input signal by identifying signal peaks and determining the signal peak magnitudes. A window function in combination with the gain ratio is applied to a portion of the input stream having a peak signal to create a cancellation pulse to be applied to that peak signal. The cancellation pulse phase is aligned with the signal phase, thereby causing minimal phase distortion in the resultant output signal and accurate peak cancellation. The cancellation pulse can also include a finite impulse response filter portion to efficiently handle wide bandwidth signals. The hardware may be configured to process multiple signal streams in parallel to reduce hardware requirements. An algorithm can determine the effect of multiple corrections to the input stream to avoid overcorrection in the signal processing process.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Applicant: Texas Instruments, Inc.
    Inventor: Hardik Prakash GANDHI
  • Patent number: 7728436
    Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: June 1, 2010
    Assignees: IMEC, Texas Instruments Inc.
    Inventors: Caroline Whelan, Victor Sutcliffe
  • Publication number: 20090280740
    Abstract: An audience and speaker interactive communications system is described. In one embodiment, it includes a server coupled to a loudspeaker, which server includes an application module for receiving and decoding speech samples and transmitting the speech samples to a loudspeaker over an unlicensed wireless communication frequency spectrum. The system also includes a mobile communications device with a connectivity application for gaining access to the server over an unlicensed wireless communication frequency spectrum as well as a client application module for encoding and transmitting speech samples to the server.
    Type: Application
    Filed: May 9, 2008
    Publication date: November 12, 2009
    Applicant: Texas Instruments Inc.
    Inventors: Phanish Hanagal Srinivasa Rao, Sherin Sasidharan, Narendran Rajan M.
  • Publication number: 20090256212
    Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 15, 2009
    Applicant: Texas Instruments, Inc.
    Inventors: Marie Denison, Taylor Rice Efland
  • Publication number: 20090228856
    Abstract: A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 10, 2009
    Applicant: Texas Instruments Inc.
    Inventor: Young-Joon Park
  • Publication number: 20090194801
    Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 6, 2009
    Applicant: Texas Instruments Inc.
    Inventors: Francis Gabriel Celii, Robert Kraft, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Theodore S. Moise
  • Publication number: 20090161410
    Abstract: The present disclosure provides a seven transistor static random access memory (7T SRAM) cell. In one embodiment, the 7T SRAM cell includes a pair of cross-coupled inverters configured to provide a memory element having first and second storage nodes. The 7T SRAM cell also includes a Read isolation transistor having a control element connected to one of the storage nodes of the cross-coupled transistor inverters and configured to provide a buffered Read output. The 7T SRAM cell further includes a Read pass gate transistor controlled by a Read word line and connected between the Read isolation transistor and a read bit line. Additionally, the 7T SRAM cell still further includes a Write pass gate transistor controlled by a Write word line and connected between one of the storage nodes of the cross-coupled inverters and a Write bit line to write either state of the memory element.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Applicant: Texas Instruments Inc.
    Inventor: Theodore W. Houston