Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a masking layer over a semiconductor substrate in a first active region and a second active region of a semiconductor device, patterning the masking layer to expose the semiconductor substrate in the first active region, and subjecting exposed portions of the semiconductor substrate to a nitrogen containing plasma, thereby forming a first layer of gate dielectric material over the semiconductor substrate in the first active region.

Abstract: A method for manufacturing a semiconductive device comprising forming a mask for a semiconductive device structure over a layer of a semiconductor substrate and partially etching the layer to form lateral and vertical surfaces. Thicknesses of one to several atomic diameters of atoms that comprise said layer are removed from the lateral surfaces and the vertical surfaces that are located under the mask to form a target dimension of a semiconductive device structure.

Abstract: The invention provides, one aspect, a method of fabricating a semiconductor device. In one aspect, the method includes forming a carbide layer over a gate electrode and depositing a pre-metal dielectric layer over the carbide layer. The method provides a significant reduction in NBTI drift.

Abstract: An integrated circuit comprising interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The dummy-fill-structures form a plurality of fiducials, each of the fiducials being located in a different region of the layer. Each fiducial comprises a pre-defined recognition pattern that is different from every other fiducial in adjacent regions of the layer.

Abstract: A method of detecting interconnect defects in a semiconductor device. The method comprises positioning a portion of a semiconductor substrate, having a plurality of interconnects, in a field of view of an inspection tool. A voltage contrast image of the portion is produced. The voltage contrast image is obtained using a collection field that is at least about 1 percent different than an incident field. The method further comprises using the voltage contrast image to determine defective ones of the interconnects.

Abstract: The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure over a substrate, the gate structure including a gate electrode located over a nitrided gate dielectric, and forming a nitrided region over a sidewall of the nitrided gate dielectric.

Abstract: The present invention provides a method for removing residue from a cavity during the formation of an interconnect structure, a method for manufacturing an interconnect structure using the same, and a method for manufacturing an integrated circuit using the same. The method for removing residue from a cavity during the formation of an interconnect structure, among other steps, may include subjecting residue (410) having an embedded metal therein located within a cavity (310) in a dielectric layer (240) and over at least a portion of a conductive feature (220) to a short duration oxidation process so as to oxidize a substantial portion of the embedded metal, and removing the residue (410) containing the oxidized embedded metal using an etch process.

Abstract: Disclosed herein are a system and method for designing digital circuits. In some embodiments, the digital circuits include processors having dedicated messaging hardware that enable processor cores to minimize interrupt activity related to inter-core communications. The messaging hardware receives and parses any message in its entirety prior to passing the contents of the message on to the digital circuit. In other embodiments, the digital circuit functionalities are partitioned across individual cores to enable parallel execution. Each core may be provided with standardized messaging hardware that shields internal implementation details from all other cores. This modular approach accelerates development and testing, and renders parallel circuit design to more efficiently attain feasible speedups. These digital circuit cores may be homogenous or heterogeneous.

Abstract: The invention provides a method of fabricating a semiconductive device. In one aspect, the method comprises heating a gas mixture [225] comprising chlorohydrocarbon having a general formula of CxHxClx, wherein x=2, 3, or 4. The chlorohydrocarbon is heated in a first chamber 210 to a first temperature that substantially disassociates the chlorohydro-carbon. The substantially disassociated chlorohydrocarbon is used to form a film on a semiconductive substrate [235] that is located in a second chamber [215].

Abstract: The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.

Abstract: The present invention provides an offset balancer for use with a differential mixer employing a wireless reception and an offset quantifier configured to indicate an existing DC offset of the mixer corresponding to an existing second-order intercept point applicable to the wireless reception. In one embodiment, the offset balancer includes an offset adjuster coupled to the offset quantifier and configured to provide an offset adjustment to the existing DC offset based on increasing the existing second-order intercept point.

Abstract: The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner 310.

Abstract: The present invention provides a body bias coordinator for use with a transistor employing a body region. In one embodiment, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor. These embodiments improve transistor active and passive performance, permit smaller transistor sizing and reduce leakage current.

Abstract: A method is described for forming an at least partially silicided contact. In one embodiment, a hardmask is deposited over a contact. A coating of sacrificial material is then provided on top of the hardmask. The sacrificial material coating is etched back until the top of the contact is exposed. The contact is then opened, the sacrificial material is removed, and a silicidation of the contact is performed.

Abstract: The present invention provides an image-rejecting channel estimator for use with an orthogonal frequency division multiplex (OFDM) receiver employing scattered pilot channel estimates. In one embodiment, the image-rejecting channel estimator includes an estimation interpolator configured to provide channel estimates through time interpolation and frequency interpolation employing the scattered pilot channel estimates. The image-rejecting channel estimator also includes an image-rejection formatter coupled to the estimation interpolator and configured to provide image-rejection filtering to suppress an image in an output spectrum of the channel estimates from at least one of the time interpolation and frequency interpolation.

Abstract: The present invention provides a thermostatic biasing controller for use with an integrated circuit. In one embodiment, the thermostatic biasing controller includes a temperature sensing unit configured to determine an operating temperature of the integrated circuit. Additionally, the thermostatic biasing controller also includes a voltage controlling unit coupled to the temperature sensing unit and configured to provide a back-bias voltage corresponding to the operating temperature based on reducing a quiescent current of the integrated circuit.

Abstract: A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with the columns, (3) a high voltage power supply configured to supply a high supply voltage, (4) a low voltage power supply configured to supply a low supply voltage, (5) bit line precharge circuitry configured to precharge at least one of the bit lines to a first voltage and (6) standby circuitry configured to maintain a voltage of the at least one bit line at at least a second voltage, the second voltage being lower than the first voltage and higher than the low supply voltage.

Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).

Abstract: The present invention provides a method for planarizing a metal layer, and a method for manufacturing a micro pixel array. The method for planarizing the metal layer, without limitation, may include the steps of forming a metal layer over a photoresist layer, and then planarizing the metal layer using a chemical mechanical planarization process.

Abstract: The present invention provides a method for manufacturing a gate dielectric (710) that includes providing a nitrided dielectric layer (220) over a substrate (120). The nitrided dielectric layer (220) has a nonuniform concentration of nitrogen in a bulk thereof. The nitrided dielectric layer (220) is exposed to oxygen radicals (410), resulting in a reduction of the non-uniformity.