Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.

Abstract: A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.

Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.

Abstract: The present disclosure provides a seven transistor static random access memory (7T SRAM) cell. In one embodiment, the 7T SRAM cell includes a pair of cross-coupled inverters configured to provide a memory element having first and second storage nodes. The 7T SRAM cell also includes a Read isolation transistor having a control element connected to one of the storage nodes of the cross-coupled transistor inverters and configured to provide a buffered Read output. The 7T SRAM cell further includes a Read pass gate transistor controlled by a Read word line and connected between the Read isolation transistor and a read bit line. Additionally, the 7T SRAM cell still further includes a Write pass gate transistor controlled by a Write word line and connected between one of the storage nodes of the cross-coupled inverters and a Write bit line to write either state of the memory element.

Abstract: One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.

Abstract: In accordance with the teachings of the present disclosure, a method and system for controlling spatial light modulator buses are provided. In accordance with one embodiment of the present disclosure, a bus controller includes a configurable bus interface having first and second modes of operation. The first mode of operation is configured to interface with a single spatial light modulator. The second mode of operation is configured to interface in parallel with a plurality of spatial light modulators. In accordance with another embodiment of the present disclosure, a method of controlling a bus includes configuring a bus interface of a bus controller to interface in parallel with a plurality of digital micromirror devices.

Abstract: The invention provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming an NMOS gate structure over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. The method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and forming a metal alloy layer over the NMOS gate electrode. The method additionally includes incorporating the metal alloy into the NMOS gate electrode to form an NMOS gate electrode fully silicided with the metal alloy.

Abstract: Provided is a method for manufacturing a semiconductor device that includes forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode. The method further includes forming a metal layer over the gate electrode, and forming a fully silicided gate electrode using the metal layer. The fully silicided gate electrode may be formed by subjecting the gate electrode to a first anneal in a presence of the metal layer to form a silicided gate electrode, wherein a maximum temperature of the first anneal does not exceed about 340° C. The fully silicided gate electrode may further be formed by removing any unreacted portions of the metal layer after the first anneal, and subjecting the silicided gate electrode to a second anneal to form the fully silicided gate electrode subsequent to the removing. A maximum temperature of the second anneal exceeds about 400° C.

Abstract: Various systems and methods for analog to digital conversion are disclosed. For example, some embodiments of the present invention provide analog to digital conversion systems. The analog to digital conversion systems include a first integrator and a second integrator, and a first summation element and a second summation element. An output of the first summation element is electrically coupled to the first integrator, and an output of the first integrator is electrically coupled to the second integrator. An output of the second integrator is electrically coupled to the second summation element. The analog to digital conversion systems further include an analog to digital converter that is electrically coupled to the first summation element via a digital to analog converter. An input to the analog to digital conversion system is electrically coupled to the first summation element, and the input is electrically coupled to the second summation element via a kickback filter.

Abstract: A system for, and method of, enhancing I2C bus data rate and an electronic assembly including the system or the method. In one embodiment, the system includes: (1) a modulus register associable with a slave device and configured to contain a modulus and (2) data transfer logic associated with the modulus register and configured to transfer data from at least one memory location in the slave device to the I2C bus based on the modulus and a starting address and at least one acknowledgement signal received via the I2C bus.

Abstract: A system, method, and logic are disclosed for automatic hardware bus encryption/decryption. The logic receives a memory access request comprising a physical address of a memory location from a processor. The logic translates the physical address, and uses the translated physical address and a seed value in a pseudo random number generator to produce an output value. The logic then uses the output value to non-deterministically select an encryption key from a plurality of encryption keys. If the memory access request is a read operation, the logic uses the selected key to decrypt the contents of the memory location; and provides the decrypted contents to the processor. If the memory access request is a write operation, the logic uses the selected key to encrypt a value comprised in the memory access request; and writes the encrypted value in the memory location.

Abstract: A method is disclosed for device management. The method is performed in a daisy-chain system of serially inter-connected devices. Such a method may include assigning ownership of a control token to a master device, the master device being one device in the system. The method may further include receiving at the master device a request for use of the control token by a peer device in the system. If the control token is available, the control token is lent to the peer device, thereby enabling the peer device to execute a command on one or more of the devices in the system.

Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with programmable hysteresis. Such circuits include a comparator input circuit that receives two inputs to be compared. The comparator input circuit provides a first differential current output based at least in part on a difference between the first voltage input and the second voltage input. The aforementioned circuits further include a hysteresis control circuit that is operable to receive a single programmable voltage input, and to provide a second differential current output based at least in part on the comparator output and the single programmable voltage input. An output circuit is also included that sums the first differential current and the second differential current, and provides a comparator output based at least in part on the sum of the first differential current and the second differential current.

Abstract: A method is disclosed for capture, display, and analysis at a receiver-specific, per-packet level for a wireless access point. The method includes configuring an access point for a capture mode. In the capture mode, the access point captures information from a packet being processed through the access point's network stack, such as PHY or MAC layer information relevant to the access point. The method further includes encapsulating the captured information in an Ethernet packet, and tunneling the Ethernet packet with the captured information to a destination host computer. At the destination host computer, the Ethernet packet is decapsulated to obtain the captured information, which may then be displayed and/or analyzed according to well known methods.

Abstract: A method, system and device are disclosed for auto-configuration of a daisy-chain system of a plurality of serially inter-connected devices. The method includes receiving at least one rule for a configuration domain. The method further includes fetching configuration information from at least one device in the system. The method additionally includes defining the configuration domain based on the at least one rule and the configuration information, applying the configuration domain to each device in the system.

Abstract: Various systems and methods for lighting are disclosed. For example, some embodiments of the present invention provide methods for retrofitting lights. The methods include providing a solid state light bulb. The solid state light bulb includes: an LED array, a dimming control circuit, and a current regulator. The current regulator provides an LED current to the LED array. The LED current varies based on a control from the dimming control circuit. The methods further include, electrically coupling the solid state light bulb to an existing incandescent dimmer switch, and adjusting the existing incandescent dimmer switch such that the intensity of light emitted from the LED array is adjusted in proportion to the adjustment of the existing incandescent dimmer switch.

Abstract: Devices and methods are disclosed for detection and management of daisy-chain system topologies. A method is disclosed for auto-discovery and auto-enumeration. The method may be performed in a daisy-chain system of serially inter-connected devices. The method may include identifying each port of each device in a system of serially inter-connected devices, discovering each device in the system, and enumerating each device in the system.

Abstract: A package frame for use in packaging microelectromechanical devices and/or spatial light modulators comprises a frame, a stiffener, and a heat dissipater.

Abstract: Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transistors in each of the differential pairs are all electrically coupled to an upper voltage via a first load resistor. Similarly, the collectors of the second transistors in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor. Depending upon the relative values selected for the first and second load resistors, the gate operates as an AND gate or an OR gate.

Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a preamplifier circuit, a latch circuit and a current re-use circuit. The current re-use circuit applies a current to the preamplifier circuit during a transparent phase, and applies a similar current to the latch circuit during a latch phase.