Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

Abstract: Signal conditioning circuitry includes logic circuitry, a low-pass filter, and comparator circuitry. The logic circuitry is configured to compare a data unit with a preceding data unit, from a sequence of data units, and provide a logic output signal. The low-pass filter is coupled to the logic circuitry, and the low-pass filter is configured to provide a data transition density measurement for the sequence of data units based on the logic output signal. The comparator circuitry is coupled to the low-pass filter, and the comparator circuitry is configured to compare the data transition density measurement to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units.

Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.

Abstract: In an example, a system includes circuitry on a first side of an isolation barrier and circuitry on a second side of the isolation barrier, where the isolation barrier is operable to electrically isolate the first side from the second side. The system also includes a trimmed oscillator, a first transmitter, and a first receiver on the first side, the trimmed oscillator coupled to the first transmitter. The system includes a tunable oscillator, a second transmitter, and a second receiver on the second side, the tunable oscillator coupled to the second receiver and the second transmitter. In the system, the first side is configured to transmit a training sequence to the second side, and the second side is configured to tune the tunable oscillator based on the training sequence.

Abstract: An input/output (I/O) interface includes a resistance-to-current (R/I) converter; an internal resistor; first, second, and third current sources; first and second diodes; and a comparator. The R/I converter is coupled to an I/O pin and generates an output current based on an external resistance at the I/O pin during an analog operating mode. The internal resistor is coupled to the I/O pin and to ground. The first current source is coupled to the R/I converter circuit. The first diode is coupled to the R/I converter and to the I/O pin. The second current source is coupled to the R/I converter and the first diode and to ground. The second diode is coupled to the I/O pin and to the third current source. The comparator has inputs coupled to the I/O pin and to a reference voltage, and outputs a control signal indicative of a digital operating mode.

Abstract: A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.

Abstract: A method includes attaching a first portion of a preformed metal micro-wire to a multilayer structure. The preformed metal micro-wire has a diameter of 10 microns or less. The method also includes attaching a second portion of the preformed metal micro-wire to the multilayer structure.

Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customer's system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: Methods of encoding a video stream in a video encoder and decoding an encoded video stream in a video decoder using a low complexity large transform are provided. An encoding method includes receiving an n×n residual block in a transform component of the video encoder, and transforming the n×n residual block using an n×n transform to generate an n×n transform coefficient block, wherein the n×n transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) discrete cosine transforms, wherein m<n. A decoding method includes receiving an n×n transform coefficient block in an inverse transform component of the video decoder, and applying an n×n inverse transform to the n×n transform coefficient block to reconstruct an n×n residual block, wherein the n×n inverse transform is based on (n/m*n/m) m×m Hadamard transforms and (m*m) (n/m)×(n/m) inverse discrete cosine transforms, wherein m<n.

Abstract: Methods and integrated circuits to process image data from single or multiple digital overlap (DOL) wide dynamic range (WDR) sensors, in which first received pixel data associated with a first exposure of a sensor image is stored in a DDR memory circuit, second received pixel data associated with a second exposure of the image is stored in the first buffer, third received pixel data associated with a third exposure of the image is stored in a second buffer, and fourth received pixel data associated with a fourth exposure of the image is provided to a merge circuit, and merged pixel data is stored in a dynamically partitioned line buffer for processing by an image pipeline circuit to facilitate interfacing multiple DOL WDR sensors in an interleaved fashion.

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

Abstract: An alkaline etching solution comprising a hydroxide salt (e.g., an alkali metal hydroxide, an ammonium hydroxide, or a combination thereof), a polyol having at least three hydroxyl (—OH) groups, and water. Also provided is a method of producing a semiconductor device by obtaining a semiconductor substrate having masked and unmasked surfaces; exposing the semiconductor substrate having the masked and unmasked surfaces to an alkaline etching solution, such that the unmasked surfaces of the substrate are anisotropically etched, wherein the alkaline etching solution comprises: a hydroxide salt; a polyol having at least three hydroxyl (—OH) groups; and water; and performing additional processing to produce the semiconductor device.

Abstract: In examples of a chopper operational amplifier, a current control circuit comprises a pair of voltage sources, each of which may be varied to generate a voltage signal of a particular value, and multiple inverters, each of which is configured to receive either a clock signal or its complement signal and one of the voltage signals. Based on these inputs, each inverter generates a control signal that is delivered to a corresponding switch in the input stage of the chopper operational amplifier to control the gate voltage of that switch. Based on the difference between the values of the voltage signals, the current control circuit operates to reduce the amplitudes of base currents induced by charge injection at the input terminals of the chopper operational amplifier.

Abstract: Systems and methods are provided for transmitting functional safety statistics within a system. A video source produces a video data stream. A functional safety system driver accumulates functional safety statistics from at least one system and writes the functional safety statistics onto an associated system memory. A display sub-system driver writes a frame of the video data stream to the system memory. The display sub-system driver formats the functional safety statistics as video data and appends the functional safety statistics to a portion of the frame of video that is reserved for the functional safety statistics. A display sub-system transmits the frame of the video data stream to a host processor, which extracts the functional safety statistics from the video frame.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: A circuit includes a first rectifier having a first rectifier input and a first rectifier output. The circuit also includes a bridge circuit and a second rectifier. The bridge circuit is coupled to the first rectifier output. The bridge circuit has first, second, third, and fourth terminals. The first and second terminals are coupled to the first rectifier output, and the third and fourth terminals are adapted to be coupled to a primary winding of a transformer. The second rectifier has a second rectifier input and a second rectifier output. The second rectifier input is adapted to be coupled to a secondary winding of the transformer.

Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

Abstract: Apparatuses and methods are disclosed for handling integrated circuits in automated testing. The handler apparatus includes an upper assembly that is selectively translatable above a testing surface and a lower bracket extending from and positioned below the upper assembly. The lower bracket forms a first opening, is selectively moveable upward and downward, and includes a rotatable finger extending downward to pick up and place an integrated circuit in a socket. The handier may further include an image sensor to detect potential error conditions, and a tool extending from the lower bracket to open and close a lid on the socket. The methods include sensing an image of an integrated circuit during certain phases of testing, analyzing the image to determine if the integrated circuit is positioned correctly, and correcting any detected error conditions before continuing with the automated testing.

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to the instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The at least one operational unit is configured to perform a table write in response to a look up table write instruction by writing at least one data element from a source data register to a specified location in a specified number of at least one table.