Abstract: An eye expander that increases the transmitter linearity of Pulse-Amplitude Modulation 4-Level (PAM4) signals having an inner eye and two outer eyes. In embodiments, the eye expander includes a semi-linear gain stage that increases the eye height of the outer eyes. In some of those embodiments, the semi-linear gain stage includes a semi-linear gain input transistor having a base or gate coupled to an input terminal and a collector or drain coupled to an output terminal, a semi-linear gain resistor coupled to the emitter or source of the semi-linear gain input transistor, and semi-linear gain transistor-resistor pairs that selectively connect the emitter or source of the semi-linear gain input transistor to ground. In some embodiments, the eye expander includes a limiting gain stage that reduces the eye height of the inner eye and a linear gain stage that increases the eye height of the inner and outer eyes.

Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

Abstract: Examples of amplifiers and associated control blocks control analog and digital gains of such an amplifier to maintain a ripple voltage at the input/virtual terminals of an internal integrator below an upper limit. Such an example amplifier comprises digital and analog processing blocks. The digital processing block receives a digital audio signal and also includes a digital gain component. The analog processing block includes an analog gain component and an output stage having a supply voltage terminal. A boost controller receives the digital audio signal, and has a digital output and a boost voltage output to output a boost voltage. A digital controller receives the digital audio signal, and has a first digital input coupled to the digital output of the boost controller and a second digital input to receive a measurement value indicative of the outputted boost voltage. Based on its inputs, the digital controller controls the digital and analog gain components.

Abstract: An example apparatus includes: first through eighth gated inverters each having inputs and outputs; a first and second inverter each having an input and an output, the output of the first inverter coupled to the input of the second gated inverter, the output of the second inverter coupled to the input of the third gated inverter; the fifth gated inverter coupled to the input of the first gated inverter and the input of the first inverter; the sixth gated inverter coupled to the input of the second inverter and the input of the fourth gated inverter; the seventh gated inverter coupled to the output of the first gated inverter and the output of the third gated inverter; the eighth gated inverter coupled to the output of the second gated inverter and the output of the fourth gated inverter; and a bus-holder circuit between the seventh and eighth gated inverter inputs.

Abstract: A capacitance sensing system senses frost and ice accumulation in an energy efficient defrost system. The capacitance sensing system comprises a first capacitor including a portion of a metal heat exchanger and a sensor electrode electrically isolated from the metal heat exchanger; a tank oscillator including a second capacitor and an inductor coupled in parallel with each other and with the first capacitor; and a circuit coupled to the tank oscillator. The circuit determines a resonant frequency of the tank oscillator, determines a capacitance value of the first capacitor based on the resonant frequency of the tank oscillator, and transmits a heater activation command in response to determining the capacitance value is greater than a threshold.

Abstract: An integrated circuit including a comparator having an enable signal input and an output and timing circuitry. The timing circuitry includes a first transistor having a control terminal, a second transistor having a control terminal, a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input, and a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

Abstract: A circuit includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor and a second transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal.

Abstract: A system comprises a photosensor and a controller. A first photoemitter transmits light onto objects at first height, a second photoemitter onto objects at second, lower height, and a third photoemitter onto objects at third, lowest height. The controller causes one of the photoemitters to transmit modulated light and the photosensor to receive reflections from a scene. The controller determines a depth map for the corresponding height based on phase differences between the transmitted and reflected light. In some examples, the system is included in an autonomous robot's navigation system. The navigation system identifies overhanging objects at the robot's top from the depth map at the first height, obstacles in the navigation route from a second depth map at the second height, and cliffs and drop-offs in the ground surface in front of the robot from the third depth map at the third height.

Abstract: In a circuit for DC-DC voltage converters, an amplifier has first and second inputs coupled to a reference voltage terminal and an output voltage terminal, respectively. A comparator has first and second inputs coupled to an amplifier output and a switching terminal, respectively. A logic circuit has inputs coupled to the comparator output and a clock terminal. A driver circuit has first and second inputs coupled to first and second logic outputs, respectively. A first transistor having a first control terminal coupled to the first driver output is coupled between a supply voltage terminal and the switching terminal. A second transistor is coupled between the switching terminal and a ground terminal, and has a second control terminal coupled to the second driver output. A threshold detection circuit is configured to provide a threshold signal responsive to a current through the second transistor crossing a current threshold.

Abstract: One example includes an integrated circuit with a sense amplifier that includes a first inverter having a first positive power terminal, a first input and a first output; and a second inverter having a second positive power terminal, a second input connected to the first output and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power terminal. A fuse is connected between the positive voltage rail and the first positive power terminal.

Abstract: A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

Abstract: Methods, apparatus, and systems to synchronize Ethernet signals are disclosed. An example apparatus includes slicer circuitry having an input coupled to interface circuitry and having an output, the slicer circuitry configured to receive an analog signal corresponding to a first Analog to Digital Converter (ADC) clock in a plurality of ADC clocks and operable to determine symbols based on the analog signal; logic circuitry to determine whether there is a symbol transition in the symbols; timing error detector circuitry to update an error value in response to the determination that there is a symbol transition; timing loop circuitry to determine a frequency of voltage oscillations based on at least the error value; and phase interpolator circuitry to change a plurality of phase parameters corresponding to the plurality of ADC clocks at a rate given by the frequency of voltage oscillations.

Abstract: An apparatus comprises: a first oscillator circuit having a first terminal and a second terminal; a second oscillator circuit having a third terminal and a fourth terminal; a first circuit having a first positive input, a first negative input, a first positive output, and a first negative output, the first positive input coupled to the first terminal, the first negative input coupled to the second terminal, the first positive output coupled to the third terminal, and the first negative output coupled to the fourth terminal; and a second circuit having a second positive input, a second negative input, a second positive output, and a second negative output, the second positive input coupled to the fourth terminal, the second negative input coupled to the third terminal, the second positive output coupled to the first terminal, and the second negative output coupled to the second terminal.

Abstract: An apparatus includes a modulation control circuit and a modulated signal generation circuit. The modulation control circuit has a control output, the modulation control circuit configured to provide, at the control output, a control signal indicative of a frequency adjustment rate of a modulated signal. The modulated signal generation circuit has a control input and an output, the control input coupled to the control output, the modulated signal generation circuit configured to provide the modulated signal at the output and adjust a modulation frequency of the modulated signal at the modulation frequency adjust rate responsive to the control signal.

Abstract: Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.

Abstract: A method is described herein. The method generally includes fetching a set of data from a memory coupled to a memory controller. The method generally includes determining a first subset of data from the set of data. The method generally includes determining a second subset of data from the set of data. The method generally includes determining a first element from the set of data. The method generally includes providing a vector including the first subset, the first element, and the second subset, wherein each element of the first subset is disposed in one portion of the vector and each element of the second subset is disposed in another portion of the vector. The method generally includes storing the vector into a register of the memory controller.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.

Abstract: An I/O module configured to operate over a range of voltage supplies includes a transmit path circuit and a receive path circuit that are each configured to convert a data signal between a core voltage domain and one of a first voltage domain (e.g., a high voltage domain) and a second voltage domain (e.g., a low voltage domain) in response to a mode select signal.

Abstract: In described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides to the transceiver and the bus monitor an instruction that indicates an instructed target address, a read/write flag, and a memory address. The transceiver provides to the first pin and the bus monitor a clock signal, and provides to the second pin and the bus monitor a message so that the message includes a messaged target address, the read/write flag, and the memory address. The bus monitor compares the instructed target address to the messaged target address, and provides a signal to the processor in response to the comparison.