Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.

Abstract: A system for determining the leakage current of a field effect transistor over temperature includes a metal oxide semiconductor field effect transistor (MOSFET) having first and second current terminals and a control terminal, wherein the first current terminal is coupled to a current measurement device. A switch is coupled to the control terminal and to a voltage source. The switch is configured to apply a voltage between a control terminal and a current terminal of the (MOSFET) responsive to a first signal, and apply approximately zero volts to the control terminal of the (MOSFET) responsive to a second signal.

Abstract: A method for inverse discrete cosine transformation (IDCT) in video coding is provided that includes receiving a transform block, identifying a region of non-zero transform coefficients in the transform block using a group significance map corresponding to the transform block, wherein any transform coefficients not in the region have a value of zero, applying a one-dimensional (1D) IDCT to the region of non-zero transform coefficients in a first direction to generate an interim results block, wherein 1D IDCT computations are not performed on transform coefficients outside the region, and applying a 1D IDCT to the interim results block in a second direction to generate a residual block.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.

Abstract: An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a centralized transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in memory devices associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use, and the technique flexible for different memory hierarchies.

Abstract: In examples, a semiconductor package comprises a wafer chip scale package (WCSP) having circuitry formed in a device side and an insulative layer above the device side. The WCSP includes one or more plated walls extending vertically to form a defined space, the one or more plated walls configured to prevent mold compound from flowing into the defined space. The WCSP includes mold compound abutting surfaces of the one or more plated walls opposing the defined space. The WCSP includes a conductive terminal coupled to the circuitry and extending from the WCSP into the defined space.

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.

Abstract: Described herein is a technology for a wakeup pattern-data stream correlation by a detector to provide a trigger condition for a microcontroller in a wakeup receiver (WuRX). For example, the detector includes a data packet layer with a plurality of index registers that are updated through sampling of data streams. A sample clock is coupled to each of the plurality of index registers to independently activate each of the plurality of index registers. A shared comparator will then compare the updated plurality of index registers to corresponding shift registers that are initialized with rotating wakeup pattern bits. Based upon a number of matching results, the detector generates a triggering signal that facilitates a low-power operating mode to a high-power operating mode change.

Abstract: A method, system, and apparatus for fault detection in a microprocessor-based system uses a serial data communication protocol for communications between a peripheral device and a controller. Peripheral device interface circuitry is adapted to intermittently receive input serial data frames from the controller using the serial communication protocol and to intermittently send output serial data frames to the controller using the serial communication protocol. Each output serial data frame includes one or more status bits representing communication status data and one or more data bits representing peripheral device data. The status bits and the data bits are serially followed by at least one fault bit that indicates whether a fault is detected during sending of the output serial data frame.

Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.

Abstract: Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.

Abstract: A system includes a battery pack having a first battery module, a second battery module, and a busbar that couples the first and second battery modules; a battery management controller having a first wireless transceiver; and a battery monitor coupled to the first battery module and to the busbar. The battery monitor includes monitoring circuitry configured to receive a first indication of a parameter of the first battery module; a second wireless transceiver configured to provide the first indication to the battery management controller via a wireless connection to the first wireless transceiver; and a busbar voltage circuit configured to receive a second indication of a voltage across the busbar, and, responsive to the second indication being greater than a voltage threshold, provide a first signal to the second wireless transceiver to cause the second wireless transceiver to be in a higher-power state.

Abstract: A transmission of information from a secondary to a primary node occurs in a plurality of transmission instances which are logical time durations. A secondary node receives an allocation of periodic transmission instances for a scheduling request indicator (SRI) and an allocation if periodic transmission instances for a sounding reference signal (SRS). In a particular transmission instance allocated for the transmission of both SRS and SRI, the secondary node transmits the SRI without transmitting the SRS if the SRI indicates a pending scheduling request; otherwise, the secondary node transmits the SRS without transmitting the SRI.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

Abstract: A method for automatic exposure (AE) control is provided that includes receiving statistics for AE control for an image from an image signal processor (ISP) coupled to an image sensor generating the image, computing an exposure value at a current time t (EV(t)) using a cost function based on target characteristics of an image, wherein computation of the cost function uses the statistics, and computing AE settings for the image sensor based on EV(t).

Abstract: In some examples a method comprises forming an insulating member over a circuit on a device side of a semiconductor die, removing a portion of the insulating member to produce a cavity, and forming a seed layer on the insulating member and within the cavity. In addition, the method includes forming a conductive member on the seed layer in the cavity, wherein the conductive member comprises a plurality of layers of different metal materials. Further, the method includes removing the seed layer from atop the insulating member, outside the cavity, after forming the conductive member in the cavity such that a remaining portion of the seed layer is positioned between the conductive member and the insulating member.

Abstract: A method of operating a long term evolution (LTE) communication system on a shared frequency spectrum is disclosed. A user equipment (UE) is initialized on an LTE frequency band. A base station (eNB) monitors the shared frequency spectrum to determine if it is BUSY. The eNB transmits to the UE on the shared frequency spectrum if it is not BUSY. The eNB waits for a first time if it is BUSY and directs the UE to vacate the shared frequency spectrum after the first time.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.