Abstract: A system comprises a photosensor and a controller. A first photoemitter transmits light onto objects at first height, a second photoemitter onto objects at second, lower height, and a third photoemitter onto objects at third, lowest height. The controller causes one of the photoemitters to transmit modulated light and the photosensor to receive reflections from a scene. The controller determines a depth map for the corresponding height based on phase differences between the transmitted and reflected light. In some examples, the system is included in an autonomous robot's navigation system. The navigation system identifies overhanging objects at the robot's top from the depth map at the first height, obstacles in the navigation route from a second depth map at the second height, and cliffs and drop-offs in the ground surface in front of the robot from the third depth map at the third height.

Abstract: In a circuit for DC-DC voltage converters, an amplifier has first and second inputs coupled to a reference voltage terminal and an output voltage terminal, respectively. A comparator has first and second inputs coupled to an amplifier output and a switching terminal, respectively. A logic circuit has inputs coupled to the comparator output and a clock terminal. A driver circuit has first and second inputs coupled to first and second logic outputs, respectively. A first transistor having a first control terminal coupled to the first driver output is coupled between a supply voltage terminal and the switching terminal. A second transistor is coupled between the switching terminal and a ground terminal, and has a second control terminal coupled to the second driver output. A threshold detection circuit is configured to provide a threshold signal responsive to a current through the second transistor crossing a current threshold.

Abstract: One example includes an integrated circuit with a sense amplifier that includes a first inverter having a first positive power terminal, a first input and a first output; and a second inverter having a second positive power terminal, a second input connected to the first output and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power terminal. A fuse is connected between the positive voltage rail and the first positive power terminal.

Abstract: A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

Abstract: Methods, apparatus, and systems to synchronize Ethernet signals are disclosed. An example apparatus includes slicer circuitry having an input coupled to interface circuitry and having an output, the slicer circuitry configured to receive an analog signal corresponding to a first Analog to Digital Converter (ADC) clock in a plurality of ADC clocks and operable to determine symbols based on the analog signal; logic circuitry to determine whether there is a symbol transition in the symbols; timing error detector circuitry to update an error value in response to the determination that there is a symbol transition; timing loop circuitry to determine a frequency of voltage oscillations based on at least the error value; and phase interpolator circuitry to change a plurality of phase parameters corresponding to the plurality of ADC clocks at a rate given by the frequency of voltage oscillations.

Abstract: An apparatus comprises: a first oscillator circuit having a first terminal and a second terminal; a second oscillator circuit having a third terminal and a fourth terminal; a first circuit having a first positive input, a first negative input, a first positive output, and a first negative output, the first positive input coupled to the first terminal, the first negative input coupled to the second terminal, the first positive output coupled to the third terminal, and the first negative output coupled to the fourth terminal; and a second circuit having a second positive input, a second negative input, a second positive output, and a second negative output, the second positive input coupled to the fourth terminal, the second negative input coupled to the third terminal, the second positive output coupled to the first terminal, and the second negative output coupled to the second terminal.

Abstract: An apparatus includes a modulation control circuit and a modulated signal generation circuit. The modulation control circuit has a control output, the modulation control circuit configured to provide, at the control output, a control signal indicative of a frequency adjustment rate of a modulated signal. The modulated signal generation circuit has a control input and an output, the control input coupled to the control output, the modulated signal generation circuit configured to provide the modulated signal at the output and adjust a modulation frequency of the modulated signal at the modulation frequency adjust rate responsive to the control signal.

Abstract: Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.

Abstract: A method is described herein. The method generally includes fetching a set of data from a memory coupled to a memory controller. The method generally includes determining a first subset of data from the set of data. The method generally includes determining a second subset of data from the set of data. The method generally includes determining a first element from the set of data. The method generally includes providing a vector including the first subset, the first element, and the second subset, wherein each element of the first subset is disposed in one portion of the vector and each element of the second subset is disposed in another portion of the vector. The method generally includes storing the vector into a register of the memory controller.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.

Abstract: An I/O module configured to operate over a range of voltage supplies includes a transmit path circuit and a receive path circuit that are each configured to convert a data signal between a core voltage domain and one of a first voltage domain (e.g., a high voltage domain) and a second voltage domain (e.g., a low voltage domain) in response to a mode select signal.

Abstract: In described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides to the transceiver and the bus monitor an instruction that indicates an instructed target address, a read/write flag, and a memory address. The transceiver provides to the first pin and the bus monitor a clock signal, and provides to the second pin and the bus monitor a message so that the message includes a messaged target address, the read/write flag, and the memory address. The bus monitor compares the instructed target address to the messaged target address, and provides a signal to the processor in response to the comparison.

Abstract: A method of fabricating an integrated circuit includes forming and patterning a hardmask over a substrate such that the patterned hardmask exposes regions of the substrate. The exposed regions are etched, thereby forming trenches and a semiconductor fin between the trenches. Prior to removing the hardmask, a photoresist layer is formed and patterned, thereby exposing a section of the semiconductor fin. A dopant is implanted into the exposed section through the hardmask.

Abstract: A circuit includes first, second third, and fourth transistors coupled in series, and a control circuit coupled to the first, second, third, and fourth transistors. The control circuit includes a clock generator, a current sense circuit, and a zero current differentiation zone (ZC_DF) circuit. The clock generator is configured to generate first and second clocks. The second clock is in quadrature with the first clock. The current sense circuit is configured to sense a current flowing through the first transistor. The ZC_DF circuit is configured to define a ZC_DF interval starting at an edge of the second clock and ending at turn-on of the fourth transistor. The control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and, in DCM, turn off the first transistor during the ZC_DF interval responsive to the current flowing through the first transistor being negative.

Abstract: A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.

Abstract: A motor control system operable to control a motor includes a motor control circuit and an inverter circuit connected to the motor control circuit and configured to connect to the motor at phase output terminals. The inverter circuit, in response to one or more output control signals indicating a deceleration instruction from the motor control circuit, implements a multi-state deceleration sequence for at least one commutation state of a commutation scheme of the motor.

Abstract: An example apparatus includes: memory including machine-readable instructions; programmable circuitry configured to execute the machine-readable instructions of the memory configured to: determine a first value of power transferred to a stepper motor during a first operation of the stepper motor; determine a second value of power transferred to the stepper motor during a second operation of the stepper motor; determine a load angle of power delivered by the stepper motor during the first operation and second operation of the stepper motor based on the first value, the second value, and a stall power; and compare the load angle to a stall threshold to detect a stall of the stepper motor.

Abstract: A comparator circuit with dynamic hysteresis. A common source branch is configured to conduct a differential current at first and second intermediate outputs responsive to a differential input at first and second inputs, and a common gate branch is configured to generate a voltage at a third intermediate output responsive to the differential current at the first and second intermediate outputs. A hysteresis branch includes a hysteresis current generator including first and second replica transistors having source/drain paths coupled in parallel, and gates coupled to the first and second inputs, respectively. A hysteresis capacitor is coupled between the sources of the first and second replica transistors and the common terminal. Current mirror circuitry is coupled to the source/drain paths of the first and second replica transistors, to supply a hysteresis current responsive to the absence of current conducted by the parallel first and second replica transistors.

Abstract: A semiconductor device can include first and second conductive layers that can be positioned over a substrate, and at least one dielectric layer between the first and second conductive layers. The at least one dielectric layer can be positioned over at least a portion of the second conductive layer, and the first conductive layer can be positioned over a portion of the least one dielectric layer. The semiconductor device can further include a third conductive layer that can be positioned over the substrate and can be conductively connected to the second conductive layer and the substrate. The third conductive layer includes a fusible link.

Abstract: An ultrasound system includes a transmit-receive switch. The transmit-receive switch includes a combined transmit-receive and return-to-zero (RTZ) path. The combined transmit-receive and RTZ path includes a transistor with a first current terminal, a second current terminal, and a control terminal. The second current terminal of the transistor is coupled to a ground node via a first switch and is coupled to a receive node via a second switch. The ultrasound system also includes a receiver front-end circuit coupled to the receive node.