Abstract: Systems and methods are provided for transmitting functional safety statistics within a system. A video source produces a video data stream. A functional safety system driver accumulates functional safety statistics from at least one system and writes the functional safety statistics onto an associated system memory. A display sub-system driver writes a frame of the video data stream to the system memory. The display sub-system driver formats the functional safety statistics as video data and appends the functional safety statistics to a portion of the frame of video that is reserved for the functional safety statistics. A display sub-system transmits the frame of the video data stream to a host processor, which extracts the functional safety statistics from the video frame.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

Abstract: Monolithic humidity sensor devices, and methods of manufacture. The devices include circuitry on or over a silicon substrate. A primary passivation barrier is formed over the circuitry with conductive vias therethrough; a capacitor, comprising metal fingers with spaces therebetween, is formed above said primary passivation barrier and electrically coupled by the conductive vias to the circuitry. A secondary passivation barrier is formed over the capacitor. A hygroscopic material layer is formed over the secondary passivation barrier, wherein the capacitor is operable to exhibit a capacitance value responsive to moisture present in the hygroscopic material layer and the circuitry is operable to generate a signal responsive to said capacitance value.

Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

Abstract: In described examples, a controller includes a converter. The converter generates a first signal responsive to an input signal. A summing block is coupled to the converter. The summing block receives the first signal and generates a second signal. A limiter is coupled to the summing block and generates a third signal responsive to the second signal and a code signal. A logic block generates a target signal responsive to the third signal. The third signal transitions to an intermediate level at a first slew rate and the third signal transitions from the intermediate level to the target signal at a second slew rate.

Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

Abstract: An integrated circuit includes a substrate having a first conductivity type. A well formed at an upper surface has a second, opposite conductivity type and a first dopant concentration. First and second STI structures are formed and a polysilicon gate structure is formed between the first and second STI structures. The polysilicon gate structure extends over a first side of the first STI structure and over a first side of the second STI structure. A first doped region is formed within the well at the upper surface and on a second side of the first STI structure and a second doped region is formed within the well at the upper surface and on a second side of the second STI structure. The first and second doped regions each have the second conductivity type and a second dopant concentration that is greater than the first dopant concentration.

Abstract: A described example includes: a semiconductor die mounted to a die pad of a package substrate, the semiconductor die having bond pads on a device side surface facing away from the die pad; bond wires coupling the bond pads of the semiconductor die to leads of the package substrate, the leads spaced from the die pad; an antenna positioned over the device side surface of the semiconductor die and having a feed line coupled between the antenna and a device side surface of the semiconductor die; and mold compound covering the semiconductor die, the bond wires, a portion of the leads, and the die side surface of the die pad, a portion of the antenna exposed from the mold compound.

Abstract: A device comprises a package substrate and a ball grid array (BGA). The package substrate encapsulates an integrated circuit (IC) die and comprises a signal launch configured to emit or receive a signal on a surface of the package substrate. The BGA is affixed to the surface and comprises a set of grounded solder balls arranged as a boundary around the signal launch. The device may further comprise a printed circuit board (PCB) substrate having a waveguide interface side opposite a secondary waveguide side and a through-hole cavity that extends from the waveguide interface side to the secondary waveguide side, perpendicular to a plane of the PCB substrate. The BGA couples the package substrate to the waveguide interface side such that the surface of the package substrate faces the through-hole cavity and the signal launch and through-hole cavity are substantially aligned.

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

Abstract: In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

Abstract: A system includes an isolated converter having a power transformer with a primary winding, a secondary winding, and an auxiliary winding. The system also includes: 1) a first switch coupled to the primary winding; 2) a switch controller coupled to the first switch; and 3) a bias power regulator circuit coupled to the auxiliary winding and the switch controller. The bias power regulator circuit includes a second switch. The bias power regulator circuit is configured to provide a bias supply output voltage to the switch controller based on a first set of modes that modulate a switching frequency of the second switch and based on a second mode in which the second switch stays off.

Abstract: Resonant DC-DC converter control circuitry includes a feedback input, a differential integrator, a resonant voltage input, a first comparator, and a second comparator. The differential integrator includes a first input, a second input, a first output, and a second output. The first input is coupled to the feedback input. The second input is coupled to a ground terminal. The first comparator includes a first input coupled to the resonant voltage input, and a second input coupled to the first output of the differential integrator. The second comparator includes a first input coupled to the resonant voltage input, and a second input coupled to the second output of the differential integrator.

Abstract: A microelectromechanical system (MEMS) structure includes at least first and second metal vias. Each of the first and second metal vias includes a respective planar metal layer having a first thickness and a respective post formed from the planar metal layer. The post has a sidewall, and the sidewall has a second thickness greater than 14% of the first thickness.

Abstract: A method includes executing, by a processor core, a first task; scheduling, by a scheduler, a second task to be executed by the processor core upon completion of executing the first task; responsive to scheduling the second task, providing, by the scheduler, a prewarming message to a memory management unit (MMU) coupled to the processor core; and responsive to receiving the prewarming message, fetching, by the MMU, a page table specified by a page table base of the prewarming message.

Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

Abstract: Methods and apparatus for parsing friendly and error resilient merge flag coding in video coding are provided. In some methods, in contrast to merging candidate list size dependent coding of the merge flag in the prior art, a merge flag is always encoded in the encoded bit stream for each inter-predicted prediction unit (PU) that is not encoded using skip mode. In some methods, in contrast to the prior art that allowed the merging candidate list to be empty, one or more zero motion vector merging candidates formatted according to the prediction type of the slice containing a PU are added to the merging candidate list if needed to ensure that the list is not empty and/or to ensure that the list contains a maximum number of merging candidates.

Abstract: An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock conf