Abstract: An improved electrically erasable semiconductor memory device of the N-channel, MOS, double level poly, programmable, read only memory or EPROM type is provided; the device is a very dense array of cells which may be electrically erased and programmed by dual injection into floating gates which are interposed between the channels and control gates. The electrical erasure or programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate to produce injection of electrons or holes. The avalanche breakdown voltage is increased by a high voltage on the row lines; the selected row line is grounded to allow erasure of a single bit or byte. The very dense array results from a simplified structure and manufacturing process which may be generally the same as prior N-channel floating gate EPROM technology.

Abstract: A novel metal-oxide-semiconductor (MOS) field effect transistor having enhanced oxide thickness at the edge of the gate electrode and having metal silicide regions in the gate electrode and source and drain areas. The enhanced oxide thickness improves interconnect-to-interconnect breakdown voltage in multilevel interconnect devices as well as minimizing gate overlap of source and drain. The metal silicide regions reduce series resistance and improve device speed and packing density.

Abstract: A power controller system for continuously supplying power to an auxillary plug-in module includes a separate power source within the module and a sensing circuit for determining whether the main power supply is within a valid range. The main system includes a DC main power supply which is coupled to the plug-in module. The sensing circuit tests to determine whether the main power supply is connected to the plug-in module for a predetermined period of time before switching this main power supply to the power using portions of the module. In the event of loss of the main power supply, either by the removal of the module or by switching off the main power supply, the sensing circuit detects this loss and the power controller system switches to the separate power source within the module.

Abstract: A digital computer system having a plurality of working registers in at least one workspace in its main memory and having a workspace pointer register for indicating the location of the workspace also has a workspace cache memory made up of registers corresponding to the working registers in the workspace of the main memory. Computer operations are implemented using the contents of the workspace cache registers whose contents are transmitted to the corresponding working registers in the workspace of the main memory in the event of a context switch. Advantageously, the architecture of this workspace system achieves high speed register-to-register operations and high speed context switching.

Abstract: The present invention relates to an automatic electrical choke, disposed inside the intake system of a gasoline engine, consisting of a bimetallic helical spring the movable end of which has an eyelet for operating the choke valve, while its second end is fastened on a fixed fastening element which is mounted inside a case, which fastening element has a ground connection and is connected electrically and thermally conducting with at least one electrical heating element with positive temperature coefficient, which is electrically connected to a current source.

Abstract: A plurality of MOS transistors are formed as an integrated semiconductor device, adjacent transistors sharing a common source/drain region which is created by the edges of inverted regions beneath the gates of the transistors. These gates are first and second level polysilicon, with the second partly overlapping the first. On the opposite ends, the source and drain regions are formed by diffusion using the oxide under the first and second level poly as the diffusion mask.

Abstract: A circuit for synchronizing the frequency and/or phase of an output frequency signal (f.sub.0) to a reference frequency signal (f.sub.ref) is disclosed. A digitally controlled oscillator produces an output frequency signal which varies dependent upon an input digital signal which also is varied. A comparator means is coupled to the oscillator and the reference signal for determining the presence or absence of a frequency or phase difference between the output frequency signal and the reference frequency signal and generates a digital signal to the oscillator indicating whether the output frequency signal should be increased or decreased. In one embodiment, the comparator means comprises an up/down counter and the digitally controlled oscillator comprises a digital-to-analog converter (DAC) coupled to an oscillator circuit. The output of the oscillator circuit (f.sub.0) is fed back through a divide by N counter circuit.

Abstract: A flexible media having a plurality of electrical conductors extending radially outward from a central portion thereof with insulative material interposed between adjacent conductors. Radially inward portions of selected ones of the conductors are placed in contact with respective ones of a first set of electrical components disposed in a first predetermined pattern and radially outward portions of the selected conductors are placed in contact with respective ones of a second set of electrical components disposed in a second predetermined pattern, the second set of components being spaced farther apart than the first set of components. In one embodiment the media is comprised of a circular elastomer material having electrical conductors disposed at equal angular intervals over the circumference of the material.

Abstract: A controlled antenna tuner comprises a power amplifier and a microprocessor, an attenuator connected to the power amplifier for selectively controlling the power output, a low pass filter connected to the power amplifier and microprocessor for channel frequency selection, a vertical standing wave ratio (VSWR) circuit inductively connected to the low pass filters output for determining the VSWR of the antenna, an impedance (magnitude) bridge and a phase detector bridge selectively connected to the low pass filter RF output and to the microprocessor for sensing the tuning status of an antenna, and an LC tuner network connected to the phase detector bridge and microprocessor, the microprocessor processing outputs of the impedance and phase detector bridges into tuning signals for the LC tuner to tune the antenna to the selected channel and storing the tuning signals for the selected channel for future use.

Abstract: A plurality of character forming segments are affixed to one surface of a front and back plate of a liquid crystal device. Three conductors affixed to one of the plates are each coupled to approximately one-third of the segment electrodes affixed to that plate. A plurality of conductors are affixed to the other plate and are each coupled to three of the segment electrodes affixed to that plate. Liquid crystal material is disposed between the two plates. By making use of the display device and a disclosed keyboard scanning circuit, an eight character position liquid crystal display device and a keyboard may be coupled to an electronic calculator chip disposed in a standard twenty-eight pin package.

Abstract: An improved ferroelectric imaging system comprises a chopper, lens system, ferroelectric detector matrix, switching matrix, temperature controlled heat sink, drive and read out electronics, video processor and display. The chopper interrupts infrared energy emanating from a scene, and the lens system focuses the chopped infrared energy on the ferroelectric detector matrix which produces electrical signals representative of the infrared energy impinging thereon. The signals are read out by the drive and read out electronics whose action is synchronized with the chopper action, processed in the video processor and displayed by the display. The ferroelectric detector matrix comprises a plurality of detector capacitor elements whose top plates are formed by conductor stripes longitudinally disposed on a dielectric of ferroelectric material and whose lower plates are a plurality of metal pads formed on the dielectric.

Abstract: A charge coupled device is disclosed which includes a plurality of stages having increased charge storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. A charge transfer channel extends through the stage. An insulating layer of non-uniform thickness lies on the first surface. The insulating layer has at least two spaced apart relatively thick portions traversing the channel, and has relatively thin portions traversing the channel throughout the spaces between the spaced apart thick portions. Phase electrodes traverse the channel such that each phase electrode overlies one relatively thick portion and one adjacent relatively thin portion of the insulating layer. A shallow dopant layer of a second-type conductivity lies throughout the channel relatively near to the first surface.

Abstract: A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Second level insulation (ZnS) is substantially thicker than the first level, and is provided with a stepped or sloped geometry under the first level gates. Input and output diodes are provided with MIS guard rings to increase breakdown voltages.

Abstract: A communications control system for enabling a small computer system, such as a personal computer, to emulate a terminal and thus to communicate with a remote system. Incoming data from the remote system is entered into a circular buffer on an interrupt basis. The communications control system alternately scans the circular buffer for newly entered data and the keyboard for operator generated messages. Any control characters are decoded and appropriate actions taken. Received alphanumeric characters are stored in a display memory for video display and in a system RAM for later retrieval and study. The display memory is optionally loaded in an intelligent wrap mode in which words are not broken on wrap around or a non-wrap mode which preserves the columns of the data as originally received. Scrolling controls enable the operator to enter a desired portion of the data stored in the system RAM into the display memory for viewing in either wrap-on or wrap-off modes.

Abstract: An electrically programmable memory array of the floating gate type is made by a process which allows the edges of the floating gates to be aligned with the edges of the control gates which also form address lines. Contacts to individual cells are not needed. These factors provide a very small cell size. The source and drain regions are formed prior to applying the first level polysilicon then covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas.

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by a triple-level polysilicon process which allows the bit lines to be formed by metal strips which have low resistance and which can cover the storage capacitors for alpha particle protection. Metal-to-silicon contacts are made through an intervening polysilicon segment which allows the underlying N+ silicon region to be much smaller than in prior cells. The polysilicon segment also prevents the occurance of problems with spiking of metal through shallow implanted N+ regions.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

Abstract: A motor protector has a tubular metal housing with open and closed ends, has a contact welded to one inner side of the housing near the closed housing end spaced from an opposite inner side of the housing, has a terminal sealed in the open housing end, and has a bimetal member extending from the terminal into the housing along the housing axis in spaced insulated relation to the housing to move into and out of engagement with the contact in response to temperature change. The protector is compact and hermetically sealed and is calibratable by housing deformation without loss of hermetic sealing. In some embodiments first and/or second heaters connected to selected motor windings via sealed terminals are compactly accommodated in the housing along respective sides of the bimetal member.

Abstract: An epitaxial layer of a narrow-gap semiconductor is deposited on a substrate comprising a wider-gap semiconductor. The opposite surface of the substrate is then illuminated with light pulses at a wavelength corresponding to the desired bandgap of the resulting material. Each pulse causes localized heating where it first encounters a material having a sufficiently narrow bandgap to be an absorber at the wavelength of illumination. This localized heating will then cause interdiffusion, producing a layer of semiconductor alloy having a bandgap intermediate between the bandgaps of the two starting materials. Repetition of this step will have the effect of moving the region of localized absorption away from the original location, and toward the film/air interface. Since the desired end product composition will be transparent to the illumination applied, the process is inherently self-limiting.

Abstract: A microcomputer system uses a standardized S-100 bus with eight bit Data In and eight bit Data Out lines, but has a sixteen bit microprocessor with sixteen bit bidirectional data input/output terminals. An arrangement of mirror image pairs of memory boards is provided to cross-connect the Data In lines and Data Out lines for one memory board compared to another, these two memory boards being accessed by the same address. A processor board containing the microprocessor connects the Data In and Data Out lines to the data input/output terminals by controllable unidirectional buffers which criss-cross the bytes on write compared to read operations.