Abstract: In described examples, a time-domain analyzer is arranged to generate an indication of a number of high-frequency events of an electrical monitor signal that includes a fundamental periodic frequency. The high-frequency events include frequencies higher than the fundamental periodic frequency. A frequency-domain analyzer is arranged to generate frequency band information in response to frequencies of the electrical monitor signal that are higher than the fundamental periodic frequency. A fault detector is arranged to monitor the indication of the number of high-frequency events and the generated frequency band information, and to generate a fault flag in response to the monitored indication of the number of high-frequency events and the generated frequency band information.

Abstract: In described examples, a DC-DC converter provides electrical power. In response to an input voltage falling below a high voltage operation threshold, the converter repeatedly performs a first normal (N) phase and a second N phase. The first N phase includes delivering power through an inductor from the input voltage. The second N phase includes coupling an input terminal of the inductor to a ground. In response to the input voltage rising above a normal operation threshold, the converter performs a first high voltage (HV) phase, then a second HV phase, then a third HV phase, then the second HV phase, and then repeats from the first HV phase. The first HV phase includes delivering power through the inductor from the input voltage and charging a flying capacitor. The second HV phase includes coupling the input terminal of the inductor to the ground. The third HV phase includes delivering power through the inductor by discharging the flying capacitor through the inductor.

Abstract: Brownout management for an audio amplification system. An audio amplification system includes audio volume control circuitry, audio sample interpolation circuitry, and brownout management circuitry. The brownout management circuitry includes brownout detection circuitry and brownout response circuitry. The brownout detection circuitry is configured to determine whether a voltage of a battery that powers the audio amplification system is below a brownout threshold, and to generate a brownout detection signal that indicates the voltage is below the brownout threshold. The brownout response circuitry is coupled to an audio output of the audio sample interpolation circuitry. The brownout response circuitry is configured to attenuate the audio samples output by the audio sample interpolation circuitry responsive to the brownout detection signal indicating that the voltage is below the brownout threshold.

Abstract: Disclosed examples include ultrasonic cleaning systems, driver integrated circuits and methods for cleaning a lens, in which an oscillating drive signal is provided to an ultrasonic transducer and the driver controls the frequency of the drive signal according to a current sense signal representing a drive current flowing in the transducer. The driver sweeps the drive signal frequency and compares the sensed current values with predetermined profiles corresponding to a clean lens and a lens with one or more known contaminants, and generates the drive signal at one or more frequencies corresponding to peaks or valleys of the sensed current values or predetermined frequencies to promote cleaning of the lens.

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Abstract: A circuit protective system with an input for sensing a reference current and an input for sensing a reference voltage. The system also has circuitry for determining an estimated energy in response to the reference current and the reference voltage and circuitry for generating a control signal responsive to the estimated energy exceeding a threshold.

Abstract: An apparatus includes a lead frame, a dam and adhesive on portions of the lead frame, and an integrated circuit die having a portion on the dam and another portion on the adhesive. The lead frame can include two portions, or two lead frames. The dam can bridge a space between the two lead frames. The dam can be smaller than the integrated circuit die in at least a width dimension of the dam relative to a width dimension of the integrated circuit die, providing that the integrated circuit die overhangs the dam on each side of the width dimension of the dam. Adhesive is located between the integrated circuit die and each lead frame, adjacent to and on each side of the dam. The dam prevents adhesive from spreading into the space between the lead frames.

Abstract: Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

Abstract: A method of forming an integrated resonator apparatus includes depositing alternating dielectric layers of lower and higher acoustic impedance materials over a substrate. First and second resonator electrodes are formed over the alternating dielectric layers, with a piezoelectric layer located between the first and second resonator electrodes. A mass bias is formed over the first and second resonator electrodes. The mass bias, first and second electrodes, piezoelectric layer, and alternating dielectric layers may be encapsulated with a plastic mold fill.

Abstract: In described examples, a first device on a first surface of a substrate is coupled to a structure arranged on a second surface of the substrate. In at least one example, a first conductor arranged on the first surface is coupled to circuitry of the first device. An elevated portion of the first conductor is supported by disposing an encapsulate and curing the encapsulate. The first conductor is severed by cutting the encapsulate and the first conductor. A second conductor is coupled to the first conductor. The second conductor is coupled to the structure arranged on the second surface of the substrate.

Abstract: Embodiments of methods and systems for supporting coexistence of multiple technologies in a Power Line Communication (PLC) network are disclosed. A long coexistence preamble sequence may be transmitted by a device that has been forced to back off the PLC channel multiple times. The long coexistence sequence provides a way for the device to request channel access from devices on the channel using other technology. The device may transmit a data packet after transmitting the long coexistence preamble sequence. A network duty cycle time may also be defined as a maximum allowed duration for nodes of the same network to access the channel. When the network duty cycle time occurs, all nodes will back off the channel for a duty cycle extended inter frame space before transmitting again. The long coexistence preamble sequence and the network duty cycle time may be used together.

Abstract: A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.

Abstract: A circuit includes a pair of high side transistors, a pair of low side transistors, a first sense resistor coupled to one of the low side transistors at a first sense node, and a second sense resistor coupled to another of the low side transistors at a second sense node. The first and second sense resistors couple together at a ground node. The circuit includes a first switch network coupled to the first sense resistor, a second switch network coupled to the second sense resistor, a first pair of switches configured to selectively provide a potential of the ground node or a potential of the first sense node as a ground potential to the first switch network, and a second pair of switches configured to selectively provide the potential of the ground node or a potential of the second sense node as a ground potential to the second switch network.

Abstract: An apparatus includes a transistor with a control terminal, a first current terminal, and a second current terminal. The apparatus also includes a charge pump coupled to the control terminal of the transistor via a first and second paths. The first path comprises a first resistor and the second path comprises a second resistor in series with a diode. The first resistor has a higher resistance value than the second resistor.

Abstract: A circuit comprises a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port; a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters.

Abstract: One example includes a device that is comprised of a die, a leadframe, and an electrically conductive material. The die includes a circuit therein. The leadframe is coupled with the die and the circuit therein. The electrically conductive material is disposed in a space above the die opposite the leadframe, the electrically conductive material being coupled to the leadframe and configured as one or more turns thereof to form at least one inductor.

Abstract: A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

Abstract: A microfabricated sensor includes a first reflector and a second reflector in a sensor cell, separated by a cavity path segment through a sensor cavity in the sensor cell. A signal window is part of the sensor cell. A signal emitter and a signal detector are disposed outside of the sensor cavity. The signal emitter is separated from the first reflector by an emitter path segment which extends through the signal window. The second reflector is separated from the second reflector by a detector path segment which extends through the signal window.

Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.